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It’s Still an Analog World: Signal and Power Integrity. 2005 MAPLD International Conference Washington, D.C. September 6, 2005. Who am I?. Shahana Aziz Senior Digital Designer (GSFC) Current Activity Hardware lead for JWST Integrated Science Instrument Module C&DH system Expertise
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It’s Still an Analog World:Signal and Power Integrity 2005 MAPLD International Conference Washington, D.C. September 6, 2005
Who am I? • Shahana Aziz • Senior Digital Designer (GSFC) • Current Activity • Hardware lead for JWST Integrated Science Instrument Module C&DH system • Expertise • Signal integrity simulation for reliable PWB designs • Focus • Ensuring reliable PWB design in high performance digital systems
What do We Want to Accomplish? • Deal (in depth) with a significant practical aspect of design integrity (power and signal integrity) • Present concrete techniques for identifying and mitigating signal and power integrity issues • Demonstrate tool operation (as time permits)
Agenda - It’s Still an Analog World • Introduction: What is Signal and Power Integrity? • Common Signal Integrity Considerations • Common Power Integrity Considerations • Guaranteeing the Design: Simulation Techniques • Simulation Examples • Comparison Examples • PCB Design Methodology • References
Agenda – What is Signal and Power Integrity? • Examples of signal integrity problems • Understanding the concerns • Definition of critical signals
GND 1.7V What is Signal and Power Integrity? (cont.)
What is Signal and Power Integrity? (cont.) Too much overshoot 3.8 V Limit • Significant and Unacceptable Over and Undershoot -0.5 V Limit Too much undershoot -0.5 V Limit From: Ed James, GSFC, ACE Signal Integrity Tuning
What is Signal and Power Integrity? (cont.) • Is 1.5 or 1.25 volts of ground bounce OK? • 1.5 volts almost 1/2 way between a logic “0” and “1” for 3.3 volt logic • High Slew • Tfall = 1.5 ns • Gnd Bounce = 0.4V • Low Slew • Tfall = 6 ns • Gnd Bounce = 0.1V See: Actel SSO Signal Integrity. PDF, Simultaneously Switching Noise and Signal Integrity
What is Signal and Power Integrity? (cont.) 1) Valid “Start” Cycle Pulse (Red) 2) When Data Bits drive low (Yellow), ground bounces causing a phantom positive glitch on “Start” locking up the system • Is every thing ok because the ambient “Functional Test” passed? Purple - 3.3 V 0.5 V/div Note more noise as AD driven “High” Green - D Gnd 0.5 V/div Note more noise as AD driven “Low” Yellow - AD 12 2 V/div Red – Start signal 0.5 V/div Note signal is nominally driven “low”, glitches represent internal chip ground
What is Signal and Power Integrity? (cont.) • Signal Integrity ensures signals are of sufficient quality to reliably transmit their required information, and do not cause problems to themselves or to other components in the system. • Signal Integrity applies to Digital, Analog and Power electronics • Signal Integrity issues are more common now because electronics are more dense and chips have faster rise times • Assuring Signal Integrity now involves more knowledge of such RF techniques as terminations, impedance matching • Major function of engineering, next to conceiving the correct design, is implementing the design correctly • Signal integrity assures the circuit design operates as intended and must be designed in. • Correct design relies on experience, best practices, analysis and simulation to ensure desired signal quality.
Designing the System Correctly • Fundamentally, signal integrity must be designed in and not "discovered" by test. • Tests verify that signals have the intended integrity. • Tests are not designed to qualify a poor design • Each designer identifies the critical signals and ensures their integrity is not compromised. • Critical signals are supported by analysis, modeling, or technical rationale justifying why they are expected to work. • Identified critical signals receive special layout attention assuring their proper functioning • Signal Integrity analysis, test results, and scope pictures should be available at the final design review
Definition of Critical Signals A line is electrically long when: Length, L (inches) > 2 X Rise Time, RT (nsec) (For a PCB built in FR4 with a di-electric constant of about 4 and speed of light is approx 6 inches/sec) When RT = 1 ns, L = 2 inches When RT = 8 ns, L = 16 inches So as edge rates get faster with newer device technologies, it is becoming more important to consider transmission line effects, termination techniques, and matched impedance in order to ensure signal integrity performance in the PWB design.
Definition of Critical Signals • Characteristics of Critical Signals: • Edges or levels whose functions would not work should they receive noise, a double clock, or a glitch. • Clocks, FIFO Read / Write, Reset, Output Enable • Analog control and / or monitor lines • Would stress parts should they over / under shoot • Rise times faster than the round trip propagation time • Source or Victims in a noise “Source” “Coupling” “Victim” analysis • Need to be stable in time to meet setup, hold, or sampling times • Cascading consequence with electrical failure or unintended output glitches
Definition of Critical Signals (cont.) • Special attention for critical signals • Hand routing, short lengths or provisions for termination resistors • Isolation from other signals by shields and / or distance • Some may not be edge sensitive but they need to be looked at to make sure that they do not over / under shoot and cause stress or that they are stable in time to meet setup and hold times
Agenda – Common Signal Integrity Considerations • Undershoot / overshoot • Ringing • Crosstalk • Timing budgets, skew, setup / hold • Mitigating Signal Integrity Issues: termination, stack-up, proper routing constraints
Common Signal Integrity Considerations • Undershoot / Overshoot • Reflections may cause voltages to go below or above the normal voltage range. • Reflections occur when the propagating signal arrives at the far end and travels back to the source. This signal can reflect a second time off the source impedance as it travels back to the head end • The undershoot/overshoot may cause damage to the ICs by damaging input protection circuitry. • In some situations reflections are required for circuit operation – i.e.., PCI bus signals, which use reflected wave signaling.
Common Signal Integrity Considerations (cont.) • Ringing • Reflections can also cause ringing effects on a signal trace. • Ringing can distort the appearance of signals, causing signal transitions to be smaller or larger at the receiver. • Can also cause damage to ICs. • Ringback problems can also cause incorrect logic switching if the voltage falls between the threshold voltage range. • Proper termination can solve overshoot / undershoot, ringing problems.
Common Signal Integrity Considerations (cont.) • Crosstalk • Signals on adjacent lines may couple to a given signal and induce crosstalk. • Mutual inductance: A magnetic field causes induced current from the driven wire to appear on the quiet wire. This mutual inductance causes positive waves to appear near the transmitter end of the quiet line (near end inductance) and negative waves at the receiver end of the transmission line (far end crosstalk). • Mutual capacitance: The coupling of two electric fields when current is injected in the quiet line proportional to the rate of change of voltage in the driver. This mutual capacitance causes positive waves near both ends of the transmission line.
Common Signal Integrity Considerations (cont.) • Crosstalk (cont.) • Crosstalk can add up if traces run parallel of each other over longer lengths on the PWB. • Crosstalk can also be induced if the trace spacing is reduced. • High density PWBs yield more crosstalk. • Crosstalk can be mitigated by laying out circuit traces appropriately – taking consideration of vertical/horizontal routing, trace width and spacing. • Need to consider capacitively coupled and inductively coupled crosstalk components
Common Signal Integrity Considerations (cont.) • Timing • Setup / hold violations can cause incorrect logic operation, glitches, metastability • Logic operating from different oscillators cause asynchronous interfaces and metastability issues • Skew of Clock and Data over temperature and / or life can result in marginal set up / hold times • Increased skew in the clock distribution system can reduce design margin
Mitigating Signal Integrity Issues • Selecting termination values • Controlling characteristic impedance • Defining the board stack-up • Constraining the routing
Selecting Termination Values • Proper termination technique reduces reflections which mitigates overshoot, undershoot, ringing problems • Termination selection must be appropriate for the application, source / driver topology • Two common termination topologies: • Source termination • End termination • Four common termination schemes: • Series termination • Parallel termination • Thevenin termination • AC termination
Selecting Termination Values (cont.) • Series Termination • Simplest termination scheme • Placed near the source/driver • Rs is chosen such that the driver output impedance, Zo + Rs will match the trace impedance, Zt • Parallel Termination • Placed near receiver. • Terminate to either Vcc or Gnd. • Not good option if need to terminate many traces, because of continuous DC current flow
Selecting Termination Values (cont.) • Thevenin Termination • Similar to parallel, but with two resistors one to Vcc and one to Gnd. • Provides pullup-pulldown function as well as termination. • AC Termination • Adds a capacitor in series with the resister near the destination. • Capacitor blocks DC current, so no steady state current as with parallel. • However capacitor might effect the rise/fall times of the signal
Clock Distribution • Special care must be taken to ensure proper clock distribution • Stubs, or excessive loading and route length can cause monotonic glitches • The use of a clock buffer should be used to provide clean, point to point routing from the clock source to each destination in the clock distribution tree • Proper termination selection will ensure quiet clock signals • Other design rules include routing clocks on a “quiet” layer (in between power planes), minimizing the number of layer switches to minimize the effects of via discontinuity • Matched length clock routing to devices ensures that skew will not decrease timing margins
Controlling Characteristic Impedance • Layer Stack up • Defines the PWB layer composition • Stack up defines trace impedance • Keeping power and ground planes together maximizes their capacitive coupling and reduces power supply noise • Extra ground planes can be used to isolate routing layers and reduce crosstalk • Controlled Impedance – provides a deterministic method of matching signal termination. It is possible to specify controlled impedance using the appropriate trace width and distance from ground. This also reduces variation in board behavior with each hardware build
Agenda – Common Power Integrity Issues • Power / Ground plane noise • Effective plane design • Decoupling, package parasitics • Power distribution system input impedance
Common Power Integrity Issues • Power Plane Noise • Noise comes from current transients caused by rapid switching. • Voltage transients cause logic problems as well as EMI problems. • Ground Bounce • Inductance in the leads of device packages cause ground bounce. • Ground bounce causes glitches in the logic inputs whenever the device outputs switch between states. • Proper bypassing techniques can be followed to mitigate ground bounce problems.
Elements in the Power Distribution System • Low impedance power planes • Decoupling capacitors • Package inductance
Power Plane Design • Need to provide low impedance return current path • Provide solid reference planes parallel to the routed signals • Consider return current amplitude when determining power plane thickness (.5, 1, 2 Oz Cu) • Pair up power and ground layers to provide additional “free” capacitance, reducing power supply noise • Use extra ground planes instead of power planes to isolate sets of routing layers. Use several vias to connect multiple ground layers. • Minimize plane splits. Split planes create return path discontinuity • This causes additional crosstalk problems • When signals travel over the split, this causes additional forward and reverse crosstalk • Remember: vias can also create the same effect of a split plane because the reference plane may change
Decoupling Considerations • Bypassing • Necessary to reduce the effects of ground bounce. • Bypass caps provide something like a regulated Power / Gnd at the device package for a short time until the inductance of the plane can be overcome. • Transient currents do not have to flow to and from the power supply then the logic device changes states, they flow to and from the caps. • Follow IC manufacturer’s guideline for appropriate bypass capacitance. Use short wide traces to route capacitor to power / gnd pins on the IC, place capacitor near component • Parallel power and ground planes provide another level of bypass capacitance. This power to ground plane capacitance has zero lead inductance, no ESR and helps reduce power / ground noise at high frequencies.
Decoupling Considerations (cont.) • Bypassing (cont.) • Select capacitors with low ESR and ESL • Consider the resonant frequency of the capacitor • Consider the capacitors effective decoupling radius: capacitors used for high frequency switching have a smaller effective radius then capacitors used for low frequency switching • For high frequency noise, place capacitors near the component being bypassed, ideally next to the power ground pins with dedicated vias for each capacitor
IC Package Effects • RTSX-S package has poor distribution of power/supply pins around the package • In the diagram shown (CQ256): • GND: GREY, QTY 19 • Core Supply: Red, QTY 9 • IO Supply: Magenta, QTY 12 • User IO: Green, QTY 201 • Inadequate power and ground pins, distributed unevenly around the package. Difficult to define design pin-out without violating SSO constraints • This effects the IO current return paths and decoupling effectiveness
IC Package Effects (cont.) • RTAXS package has superior distribution of power/supply pins around the package • In the diagram shown (CQ352): • GND: GREY, QTY 56 • Core Supply: Red, QTY 44 • IO Supply: Magenta, QTY 29 • User IO: Green, QTY 179 • Symmetrically distributed power and ground pins around the package, proportional to available IO pins. Far easier to define design pin-out without violating SSO constraints
Agenda – Simulation Techniques • Simulation tool benefits, capabilities • Types of analysis techniques • Simulation models: SPICE vs. IBIS
Guaranteeing the Design: Signal Integrity Analysis • Signal integrity analysis is about avoiding problems as opposed to fixing them. • SI analysis addresses: • Timing: • Avoid functional integrity issues • Improve timing margins, resolve clock skew issues • Signal Quality • Provide proper routing, minimizing reflections, impedance mismatch • Avoid using incorrect termination strategy and termination values • Avoid false triggering and functional instability caused by non-monotonic signals
Guaranteeing the Design: Signal Integrity Analysis (cont.) • SI analysis addresses: (cont.) • Signal quality (cont.) • Identify constraints (min / max length, impedance, no. of vias, Er, etc) necessary dielectric material and best trace length and width geometry. • Avoid crosstalk issues and improve noise margins • Avoid unsuitable layout topologies: daisy chain, star, far-end cluster • Power and Ground Distribution • Power Distribution Architecture including Decoupling Capacitor placement and sizing • Define SSO mitigation strategies • Reduce the level of EMI emission and likelihood of an EMC failure
Signal Integrity Simulation Methods • Paper, back of an envelope, best practice • Suitable for simple, slow rise time, slow bandwidth, robust and forgiving designs • Excel, Power Point, Word • Summarizing set up hold, static timing • Spice • Model circuit at transistor level, does not automatically take into account PCB parameters • Mostly used for Analog circuits • Can model digital devices
Signal Integrity Simulation Methods (cont.) • Detailed Board / System Simulations Integrated with PCB Tools • Tools import PCB layout and can simulate IO activity as well as power plane responses • Appropriate for high speed, dense and complex systems • Interconnectix Syntheis, Hyperlynx etc • Detailed PCB layout • IBIS + Spice • Speed2000 • Detailed power plane and IC power Quality
Introduction to Modeling: SPICE • SPICE simulations model a circuit at transistor level, thus SPICE models contain detailed information about the circuit and process parameters which is regarded as proprietary and IC vendors are reluctant to provide.. • Not all SPICE simulators are fully compatible. • Although SPICE simulation accuracy is typically very good, a significant limitation with this type of modeling is simulation speed. • SPICE has various simulator options that control accuracy, convergence and the algorithm type, and any options that are not consistent might give rise to poor correlation in simulation results across different simulators. IBIS is an alternative to SPICE simulation
Introduction to IBIS Models • IBIS: Input/Output Buffer Information Specification from the Electronics Industry Alliance • IBIS behavioral data is taken from actual devices. • IBIS models tend to simulate much faster than SPICE models. • IBIS Modeling provides a simple table-based buffer model for semiconductor devices. • IBIS models can be used to characterize I/V output curves, rising/falling transition waveforms, and package parasitic information of the device.
Introduction to IBIS Models (cont.) • IBIS models are intended to provide nonproprietary information about I/O buffers and are more easily available from different IC vendors • Non-convergence is eliminated in IBIS simulation. • Virtually all EDA vendors presently support IBIS models, and ease of use of these IBIS simulators is generally very good. • IBIS models for most devices are freely available over the Internet making it easy to simulate several different manufacturers’ devices on the same board.
Elements of an IBIS Model     
Elements of an IBIS Model (cont.) Element 1: Pull-down • Describes the I/V characteristics during pull-down. • Data for minimum and maximum current for given voltages. • Data is taken for -Vcc to 2Vcc as that allows a behavioral model for signal reflections caused by improper termination and overshoot and undershoot situations when the protection diodes are forward biased. Element 
Elements of an IBIS Model (cont.) Element 2: Pull-up • Describes the pull-up state of the buffer when the output drives high. • Data is entered using the formula Vtable = Vcc – Voutput • The minimum and maximum values are determined by the minimum and maximum operating temperatures, supply voltages and process variations. • Combining the highest current values with the fastest ramp time and minimum package characteristics, a fast model can be derived. A slow model can be derived by combining the lowest current with the slowest ramp time and maximum package characteristics. Element 
Elements of an IBIS Model (cont.) Element 3: GND and Power Clamps • Describes the ground and power clamp diodes. • The GND clamp curve is derived from the ground relative data gathered while the buffer is in the high-impedance state and illustrates the region where the ground clamp diode is active. The range is from -VCC to VCC. • The power clamp curve is derived from the VCC relative data gathered while the buffer is in a high impedance state and shows the region where the power clamp diode is active. This measurement ranges from VCC to 2VCC. Element 
Elements of an IBIS Model (cont.) Element 4: Ramp • Describes the ramp time for the pull-up and pull-down devices. Ensures proper AC operation of the model. • The min and max columns represent the minimum and maximum slew rates for the buffers. • The values represent the intrinsic values of the transistors with all package parasitics and external loads removed. Element 
Elements of an IBIS Model (cont.) Element 5: Package • Adds the component and package parasitics. • C_comp is the capacitance of the die itself, excluding the package capacitance. • Package characteristic resistance, inductance and capacitance are added by R_pkg, L_pkg, and C_pkg, respectively. Element 
Creating the IBIS File • A standard IBIS model file consists of three sections: • Header Info–this section contains basic information about the IBIS file and what data it provides. • Component, Package, and Pin Info –this section contains all information regarding the targeted device package, pin lists, pin operating conditions, and pin-to-buffer mapping. • V-I Behavioral Model–this section contains all data to recreate I-V curves as well as V-t transition waveforms, which describe the switching properties of the particular buffer.
Header Component Model I-V Data Example of an IBIS File