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Analog VLSI Design

Analog VLSI Design. Technology Trends. 3 Crises in VLSI Design. Power Crises. VLSI - Ever Increasing Power. Trends in Power, VDD and Current. Power/Delay Trade-Off. Leaky Transistors. 3 Strategies for Low Power. Low Power Strategies. Interconnect . Interconnect Trends.

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Analog VLSI Design

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  1. Analog VLSI Design Technology Trends

  2. 3 Crises in VLSI Design

  3. Power Crises

  4. VLSI - Ever Increasing Power

  5. Trends in Power, VDD and Current

  6. Power/Delay Trade-Off

  7. Leaky Transistors

  8. 3 Strategies for Low Power

  9. Low Power Strategies

  10. Interconnect

  11. Interconnect Trends

  12. InterconnectTrends

  13. Design Issues

  14. Coupled Noise

  15. Complexity

  16. Which Way Forward?

  17. Future Chips 2014

  18. Challenge

  19. ANALOG VLSI DESIGN Principles, Techniques, Building Blocks

  20. Is Analog VLSI Design Dead? • No, not true! • Total analog chip sales for 2002 $39 billion, 2004 ~ $48billion • 10% increase over previous year, growth predicted for next 3 years • Raw transducer output in most systems is analog in nature • Although very small %age of total chip area is analog, still a need for good design practice since analog component may be the limiting factor on overall system performance • Days of pure analog design are over, majority of systems are integrated with increased functionality in digital domain • Will attempt to introduce some hierarchy - use building block approach as for digital • Bottom Line: Ability to design both analog and digital circuits and understand interactions between the 2 domains adds dimension to your design portfolio

  21. Analog Building Blocks • Basic Blocks include Current Sources Current Mirrors Single Stage Amplifiers Differential Amplifiers & Op Amps Comparators Voltage References Data Converters Switched Capacitor Circuits

  22. CMOS Technology • MOS Market dominates worldwide chip sales (>75%) • Total MOS sales 2003/2004 ~ $250 billion • Illustrates strength of CMOS technology - feature sizes now < 0.1um • True system-level integration on a chip i.e. converters, filters, dsp processors, microcontroller cores, memory all reside on one die • >180 million transistors/chip • Decreases in feature size cause some complexities: Layout issues more important Modeling is a key issue Parasitic effects significant Power dissipation issues challenging (BiCMOS, VDD-hopping, etc)

  23. Low Power + High Speed=BiCMOS • Future of Gigascale Integration lies in BiCMOS technology • Application Example : Wireless Communications - pagers, cellular phones, laptops, palmtops • Requirement for high speed low power front end challenge for analog designers (cannot afford time and energy to digitize first) Historical Roadmap: Bipolar/CMOS • 1930’s – MOS invented, didn’t catch on, dormant for 30 yrs • 1940’s- 50’s – Bipolars invented, became dominant thru the early 70’s • 1970’s - Power consumption issues re-ignited interest in MOS • 1980 MOS/Bipolar share of market 50/50 (largely due to CMOS) • 1983 – BiCMOS invented • 1990’s – CMOS dominant • 2000’s - BiCMOS integrated into CMOS, Gigascale Integration

  24. Improvement Trends • Functionality (e.g. non-volatility, smart power) • Integration Level (e.g. components per chip, Moore’s Law) • Compactness (e.g. components/sq cm) • Speed (e.g. microprocessor clock in MHZ) • Power (e.g. laptop or cellphone battery life) • Cost (e.g. cost per function, historically decreasing) Available from scaling & tech improvements over last 30yrs

  25. Future Trends: International Technology Roadmap for Semiconductors (ITRS) • S/C industry has become a global industry in the 90’s: manufacturers, suppliers, alliances, world wide operations. Since 1992 Semiconductor Industries Association (SIA) has produced a 15year outlook on major trends in the s/c industry (ITRS) • Technical challenges identified • Solutions proposed (where possible) • Traditional is reaching fundamental limits • New materials must be introduced to further extend scaling limits Way to go: • System In a Package (SiP • P-SoC (Performance System-on-a-Chip): integration of multiple silicon technologies on a chip • Nanotechnology • Neuromorphic Systems - emulate natural signal processing (circuits operating in subthreshold/weak inversion )

  26. ITRS: Technology Working Groups (TWG’s) Purpose: To provide guidance, host and edit workshop in following areas • Design • Test • Process Integration, Devices, Structures • Front End Processes • Lithography • Interconnect • Factory Integration • Assembly & Packaging • Cross Cutting Working Groups in environment, safety, defect reduction, metrology, modeling/simulation

  27. ITRS: Example of Key Lithography-Related Characteristics • Year 99 2002 2004 2008 • DRAM pitch 180nm 130nm 110nm 70nm • MPU Gate Length 140nm 100nm 70nm 45nm What is S-o-C (system on a chip)? • S-o-C chips are often mixed-technology designs, including such diverse combinations as embedded DRAM, high-performance or low-power logic, analog, RF, esoteric technologies like Micro-Electro Mechanical Systems (MEMS) , optical input/output. • Time-to-market for particular application-specific capability is key • Product families will be developed around specific SoC architectures and many SoC designs customized for target markets by programming part (using software, FPGA, Flash, and others). • Category of SoC is referred to as a programmable platform. The design tools and technologies needed to assemble, verify, and program such embedded SoC’s will present a major challenge over the next decade.

  28. Interconnect Working Group • Function of interconnect is to distribute clock and other signals and to provide power/ground • Requirement for interconnect is to meet the high-speed transmission needs of chips despite further scaling of feature sizes. • As supply voltage reduced, cross-talk an issue, near term solution is use of thinner copper metallization to lower line-to-line capacitance. • Although copper-containing chips introduced in 1998, copper must be combined with new insulator materials. Introduction of new low k dielectrics, CVD metal/barrier/seed layers, and additional elements for SoC, provide process integration challenges. • Emerging system-in-a-package (SiP) and system-on-a-chip, or SoC • For long term, material innovation with traditional scaling will no longer satisfy performance requirements. New design or technology solutions (such as coplanar waveguides, free space RF, optical interconnect) will be needed to overcome the performance limitations of traditional interconnect.

  29. Analog VLSI Design ECE567 Spr 2008 • Professor: Dr. Abby Ilumoka, Room UT 235, Ph: (860) - 768 - 5231 • Email: ILUMOKANW@MAIL.HARTFORD.EDU • Class Time: Mon 5.45pm – 8.15pm • Office Hrs: Tues Thur 10.50am – 12.10pm, Mon 4-5pm, Wed 11-11.30am • Credits: 3 credits • Objectives:Course deals with design principles and techniques for high performance analog IC’s implemented in CMOS technology. Although analog design appears to be much less systematic than digital, course highlights good design principles to simplify process. Course Text & Materials: 1. Analog Integrated Circuit Design by Johns & Martin, Wiley 1997 2. CMOS Circuit design layout & Simulation by Baker, Li & Boyce, IEEE Press, 1998 3. Specified journal & conference papers Grading Policy and Exam Dates: 4 Exams - 4 X 25% = 100 % Laboratory/ Design Assignments (bonus max 10%) TOTAL 100% Spr 2008 Exam Dates: Exam 1 Mon Feb 18 Exam 2 Mon Mar 24 Exam 3 Mon Apr 21 Exam 4 Mon May 12

  30. TOPICS • 1. Advanced MOS Modeling • - Short Channel Effects • - Sub-threshold Operation • - Leakage Currents • 2. Processing and Layout for CMOS Analog Circuits • 3. Fundamental Building Blocks of Analog IC’s • - MOS Current Mirrors • - Single Stage Amps • - SPICE Simulation Examples • 4. Design of the 2 stage CMOS Op Amp: Op Amp I • 5. Design of the 2 stage CMOS Op Amp: Op Amp II 6. Additional Analog Building Blocks - Comparators • - Sample and Hold circuits • - Switched capacitor Circuits • 7. Data Converters A-D and D-A • 8. Design Refinement & Optimization Techniques • 9.Noise Analysis and Modeling

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