Analog Digital VLSI Design discovery.bits-pilani.ac

1. Analog Digital VLSI Designhttp://discovery.bits-pilani.ac.in/discipline/eee/agupta/advd/advd.htm

2. Handout

7. Previous knowledge Digital electronics Micro electronic circuits Electronic devices

8. Objective VLSI circuit design and verification Silicon implementation Usage of EDA tools

9. Goals of this Course Learn to design and analyze state-of-the-art digital VLSI chips using CMOS technology Understand design issues at the layout, transistor, logic and register-transfer levels Performance analysis and optimization Use commercial design software in the lab Complexity management Understand the complete design flow

10. VLSI DESIGN

11. What is VLSI design? A way to design electronic circuits Dimensionally �micron, submicron, nano range

12. Why VLSI imp? Current day technology Micro electronics creeping in all disciplines--- (merger of various disciplines in system design) Bio medical/ health�brain mapping, artificial intelligence Electromechanical systems�robotics Communication, Smart and secure homes, Identification , vehicular electronics, process control

13. Uniqueness of VLSI Design HIGH INTEGRATION DENSITY INTERCONNECT CROSS TALK, MISMATCH (ON CHIP, DIE TO DIE), COMPLEX DESIGNS, DESIGN VERIFICATION & TESTABILITY DESIGN RULES are important design issues now FAST CHANGING TECHNOLOGY PORTING DESIGN TO NEW TECH GENERATION , NEW SET OF DESIGN RULES �make design indep. of design rules leverage existing work: programs ,building blocks

14. Design Strategies Design is a continuous tradeoff to achieve performance specs with adequate results in all the other parameters. Design Parameters By Which Design Success Is Measured: Performance Specs - function, timing, speed, power Size of Die - manufacturing cost Time to Design - engineering cost and schedule Ease of Test Generation & Testability - engineering cost, manufacturing cost, schedule Manufacturability - resilient to circuit/process variabilities

16. VLSI design flow--Y chart (D.GJASKI)

19. VLSI Design Styles Programmable Logic Devices Programmable Logic Device (PLD) Field Programmable Gate Array (FPGA) Gate Array Standard Cell (Semi-Custom Design) Full-Custom Design

20. IMPACT OF DIFFERENT VLSI DESIGN STYLES ON DESIGNCYCLE TIME AND ACHIEVABLE CHIP PERFORMANCE

21. PERFORMANCE IMPROVEMENT OF A VLSI PRODUCT FOR EACH NEW GENERATION OF MANUFACTURING TECHNOLOGY

22. Analog Design Only Full custom Fully handcrafted design Each design requires specific performance Limited automation possible Lack of Automation supporting CAD tools

23. DIGITAL CMOS CHIP DESIGN OPTIONS

24. Field Programmable Gate Array (FPGA)

25. Introduction User / Field Programmability. Array of logic cells connected via routing channels. Special I/O cells. Logic cells are mainly lookup tables (LUT) with associated registers. Interconnection on SRAM basis or antifuse elements.

28. XC4000E Configurable Logic Blocks 2 Four-input function generators (Look Up Tables) - 16x1 RAM or Logic function 2 Registers - Each can be configured as Flip Flop or Latch - Independent clock polarity - Synchronous and asynchronous Set/Reset

29. Look Up Tables Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB Example:

30. XC4000X I/O Block Diagram

31. Xilinx FPGA Routing 1) Fast Direct Interconnect - CLB to CLB 2) General Purpose Interconnect - Uses switch matrix

32. Design Flow

33. Gate Array

34. Gate Array In view of the fast prototyping capability, the gate array (GA) comes after the FPGA. Design implementation of FPGA chip is done with user programming, Gate array is done with metal mask design and processing. Gate array implementation requires a two-step manufacturing process: The first phase, which is based on generic (standard) masks, results in an array of uncommitted transistors on each GA chip. These uncommitted chips can be customized later, which is completed by defining the metal interconnects between the transistors of the array

36. Channeled vs. Channel-less (SoG) Approaches

37. Small Section of a Semi-custom Base Array Without Interconnect

38. Section of Semi-custom Array with Single Level Metal Interconnect

39. The GA chip utilization factor is higher than that of FPGA. The used chip area divided by the total chip area. Chip speed is also higher. More customized design can be achieved with metal mask designs. Current gate array chips can implement as many as hundreds of thousands of logic gates.

40. Standard Cell Based DesignCBIC

41. CBIC One of the most prevalent custom design styles. Also called semi-custom design style. Requires development of a full custom mask set. Basic idea: All of the commonly used logic cells are developed, characterized, and stored in a standard cell library. A typical library may contain a few hundred cells including inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches, and flip-flops.

42. Characteristic of the Cells Each cell is designed with a fixed height. To enable automated placement of the cells, and Routing of inter-cell connections. A number of cells can be abutted side-by-side to form rows. The power and ground rails typically run parallel to the upper and lower boundaries of the cell. Neighboring cells share a common power and ground bus. nMOS transistors are located closer to the ground rail while the pMOS transistors are placed closer to the power rail. The input and output pins are located on the upper and lower boundaries of the cell.

43. Standard Cells

44. Standard Cell Layout

45. Floor-plan for Standard Cell Design Inside the I/O frame which is reserved for I/O cells, the chip area contains rows or columns of standard cells. Between cell rows are channels for dedicated inter-cell routing. Over-the-cell routing is also possible. The physical design and layout of logic cells ensure that When placed into rows, their heights match. Neighboring cells can be abutted side-by-side, which provides natural connections for power and ground lines in each row.

47. Full Custom Design

48. Introduction The standard-cells based design is often called semi custom design. The cells are pre-designed for general use and the same cells are utilized in many different chip designs. In the full custom design, the entire mask design is done anew without use of any library. The development cost of such a design style is prohibitively high. The concept of design reuse is becoming popular in order to reduce design cycle time and cost.

49. Contd. The most rigorous full custom design can be the design of a memory cell. Static or dynamic. Since the same layout design is replicated, there would not be any alternative to high density memory chip design. For logic chip design, a good compromise can be achieved by using a combination of different design styles on the same chip. Standard cells, data-path cells and PLAs.

50. In real full-custom layout in which the geometry, orientation and placement of every transistor is done individually by the designer, Design productivity is usually very low. Typically 10 to 20 transistors per day, per designer. Full-custom layout

51. Continued In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost. Exceptions to this include the design of high-volume products such as memory chips, high-performance microprocessors and FPGA masters. Next slide shows the full layout of the Intel 486 ?P chip. Good example of a hybrid full-custom design.

53. Small Section of a Typical Full Custom Layout

54. Comparison Among Various Design Styles

55. Design quality ACHIEVE SPECIFICATIONS (Static & Dynamic) DIE SIZE POWER DISSIPATION TESTABILITY YIELD AND MANUFACTURABILITY RELIABILITY TECHNOLOGY UPDATABLE

56. -> TESTABILITY + generation of good test vectors + availablity of reliable test fixture at speed + design of testable chip -> YIELD AND MANUFACTURABILITY + functional yield + parametric yield Contd.

57. Contd. ->RELIABILITY + premature aging (Infant mortality) + ESD/EOS + latchup + on-chip noise and crosstalk + power and ground bouncing ->TECHNOLOGY UPDATABLE + Easily updated to new design rules

58. Some other important issues Highly complex design--- structured design strategies Packaging

60. Structured Design Strategies Strategies common for complex hardware and software projects. -> Hierarchy: Subdivide the design into many levels of sub-modules -> Modularity: Define sub-modules unambiguously & well defined interfaces -> Regularity: Subdivide to max number of similar sub-modules at each level -> Locality: Max local connections, keeping critical paths within module boundaries

61. Regularity Design the chip hierarchy into identical or similar modules Extended use of a single design simplifies the design process Regularity can exist at all levels of design hierarchy Circuit Level: uniform transistor sizes rather than manually optimizing each device. Logic Level: identical gate structures rather than customize every gate. Architecture Level: construct architectures that use a number of identical processor structures

62. Modularity ADDS TO HIERARCHY AND REGULARITY THE QUALITIES OF WELL DEFINED FUNCTIONS AND INTERFACES -> Unambiguous functions -> Well defined behavioral, structural, and physical interfaces -> Enables modules to be individually designed and evaluated.

63. Locality TIME LOCALITY: modules see a common clock and synchronous timing is applied. Robust clock generation and distribution is critical Critical paths, where possible, are to be kept within module boundaries Any global module to module signal should have an entire clock cycle to traverse the chip. Replicate logic, if necessary, to alleviate cross-chip crossings. Locate modules in layout to minimize large or "global" routes between modules.

64. Design for manufacturability Design goal: All fabricated circuits meet all performance specs under all operating conditions. Impediments: Random variations in fabrication process. Random variations in operating conditions, e.g. VDD, Tambient.

65. Reality: Excessive deviations of performance cause yield loss and increase the unit cost of the chip. Why DFM important?

66. DFM Issues: 1. Parametric yield estimation. 2. Parametric yield maximization. 3. Worst-case analysis. 4. Variability Minimization.

67. DFM DFM Practice: Consider the effects of expected randomness in processing and operating conditions early in the design process. Circuit made as insensitive to these variations as is practical. Design to performance specs with sufficient margins that a large fraction of the manufactured chips pass the chip acceptance criteria.

68. Packaging Technology Include important package related parasitics in the chip design and simulation Package Power & Ground Planes On-chip power and ground busses Bond Wire Lengths -> on-chip inductive effects Thermal Resistance -> temp rise due to on-chip power dissipation Package Cost

69. Important package design concerns: hermetic seals to prevent penetration of moisture thermal conductivity thermal expansion coefficient pin density parasitic inductance and capacitance alpha-paricle protection (memories)

70. Package types

72. Custom integration An integrated circuit that requires a full set of masks specifically designed for a particular function or application. A custom IC is usually developed for a specific customer and may have to withstand harsh environments .

73. Why consider custom integration? There are a number of reasons why developing a custom Integrated Circuit is an appropriate and often essential ingredient to the development of a successful product

74. Reasons Size. The continued market demand to reduce the size of electronic devices, in particular portable and hand-held devices, requires ever higher levels of integration. Replacing functions requiring the use of a number of discrete components with one IC helps achieve this goal.

75. Contd. Performance. By utilizing the superior matching and tracking characteristics of integrated circuit components, manual adjustment of circuit parameters can often be eliminated, while maintaining tighter spread on key system performance specs over the full range of operating conditions. Additionally, critical or high-precision specs can be trimmed at wafer test.

76. Contd. Cost. Replacing a number of discrete components with a pre-tested IC significantly reduces the test time and the number of rejects. For large production quantities the initial development cost will be amortized in a short period of time, resulting in a lower cost per unit.

77. Contd. Reliability. An IC is significantly more reliable than a PCB populated with the devices necessary to provide the equivalent functionality using discrete components or multiple IC's.

78. Contd. Copy protection. This can be the most important incentive to consider custom integration. Simple hardware copying is prevented because of the exclusivity of the custom IC.

79. What are the fab. technology options? The three principal technologies which are readily accessible for custom integration are Biploar, CMOS and BiCMOS Choice between using a prefabricated semi-custom array or undertaking a full custom development

80. CMOS processing N-WELL P-WELL TWIN-TUB

81. Wafer preparation defect free single crystalline lightly doped WAFER. Metallurgical grade silicon-electronic grade silicon(99.99% pure) Single crystalline structure obtained by melting and then cooling ---czochralski method Ingot cut into wafers using diamond saw Wafers are than polished to mirror finish

82. Process involved Photolithography Deposition Oxidation Etching Diffusion/ion implantation

83. General Principles Technology changes fast, so it is important to understand the general principles which would span technology generations optimization, tradeoffs work as part of a group leverage existing work: programs ,building blocks Concepts remain the same: Example: relays -> tubes -> bipolar transistors -> MOS transistors