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ADVANCED ANALOG VLSI DESIGN CENTER

ADVANCED ANALOG VLSI DESIGN CENTER. ADVANCED ANALOG VLSI DESIGN CENTER. VLSI DESIGN CYCLE. VLSI DESIGN GUIDELINES. The L-Edit screen. Design Rule Checker. Menu Bar. Drawing Tools. Locator. Layer Palette. Work Area. Origin Marker.

JasminFlorian
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ADVANCED ANALOG VLSI DESIGN CENTER

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  1. ADVANCED ANALOG VLSI DESIGN CENTER

  2. ADVANCED ANALOG VLSI DESIGN CENTER

  3. VLSI DESIGN CYCLE

  4. VLSI DESIGN GUIDELINES

  5. The L-Edit screen Design Rule Checker Menu Bar Drawing Tools Locator Layer Palette Work Area Origin Marker

  6. 1.2 MICRON DOUBLE POLY, DOUBLE METAL ISO-CMOS DESIGN RULES 2.1.2 2.1.1 2.2 ploy 9.2 11.1 11.3 11.2 M1 9.3 9.1 2.5 2.3 M1 M1 PA PA M2 NA NA 2.4 2.6 M2

  7. 1.2 MICRON DOUBLE POLY, DOUBLE METAL ISO-CMOS DESIGN RULE 8.2.1 8.1 8.1.1 8.2.2 8.3.1 A V V 10.1 10.1 8.3.4 8.3.2 10.5 10.2 10.3 V V V M1 V 10.4 10.8 10.9.2 10.9.1 V V V V 10.7 10.6 10.6

  8. 1.2 MICRON DOUBLE POLY, DOUBLE METAL ISO-CMOS DESIGN RULE 1.1 1.2 PA 1.3 A 6.1 7.1

  9. Large Signal Equivalent Ckt

  10. A Simple Way to View Digital Ron

  11. Example No 1.

  12. Example No 2.

  13. MOSFET Layout1.1 PMOSFET Layout

  14. MOSFET Layout1.2 NMOSFET Layout

  15. INVERTERS

  16. INVERTER INTRO

  17. INV INTRO - NOISE MARGIN

  18. INVERTER POWER

  19. MOSFET Scaling

  20. Three State Buffers Non-inverting buffer's timing waveform 100 D E F "Z" "Z"

  21. Three State Buffer- The Third State Logic States: "0", "1" Don't Care/Don't Know State: "X" (must be some value in real circuit!) Third State: "Z" — high impedance — infinite resistance, no connection Tri-state gates: output values are "0", "1", and "Z" additional input: output enable (E) When E is high, this gate is a non-inverting "buffer" When E is low, it is as though the gate was disconnected from the output! This allows more than one gate to be connected to the same output wire, as long as only one has its output enabled at the same time

  22. Example of cross-sectional view

  23. MOSFET Parasitics

  24. Example No 3.

  25. Example No 4.

  26. SUPER BUFFER

  27. SUPER BUFFER Con’t

  28. SUPER BUFFER Con’t ·(LN() - 1) = Cd / Cg =x

  29. SUPER BUFFER EX 5

  30. CLOCK DISTRIBUTION

  31. VLSI I/O

  32. Transmission Gate

  33. Transmission GateExtraction

  34. Transmission or t-gates

  35. T-gate Example Ckts

  36. Selector Demultiplexer Selector: Choose I0 if S = 0 Choose I1 if S = 1 Demultiplexer: I to Z0 if S = 0 I to Z1 if S = 1

  37. Well-formed Switching Networks Problem with the Demux implementation: multiple outputs, but only one connected to the input! The fix: additional logic to drive every output to a known value Never allow outputs to "float"

  38. D-type flip-flop Q Q Bar

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