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ELEC 7770 Advanced VLSI Design Spring 2007 VLSI System DFT PowerPoint Presentation
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ELEC 7770 Advanced VLSI Design Spring 2007 VLSI System DFT

ELEC 7770 Advanced VLSI Design Spring 2007 VLSI System DFT

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ELEC 7770 Advanced VLSI Design Spring 2007 VLSI System DFT

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  1. ELEC 7770Advanced VLSI DesignSpring 2007VLSI System DFT Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07 ELEC 7770: Advanced VLSI Design (Agrawal)

  2. SOC Design: A DFT Problem • Given the changing scenario in VLSI: • Mixed-signal circuits • System-on-a-chip • Multi-chip modules • Intellectual property (IP) cores • A system must be designed for testability. ELEC 7770: Advanced VLSI Design (Agrawal)

  3. Conventional Test:In-Circuit Test (ICT) • A bed-of-nails fixture provides direct access to each chip on the board. • Advantages: Thorough test for devices; good interconnect test. • Limitations: • Works best when analog and digital functions are implemented on separate chips. • Devices must be designed for backdriving protection. • Not applicable to system-on-a-chip (SOC). • Disadvantages: • High cost and inflexibility of test fixture. • System test must check for timing. ELEC 7770: Advanced VLSI Design (Agrawal)

  4. Tested parts In-circuit test (ICT) Easy test access Bulky Slow High assembly cost High reliability Fast interconnects Low cost Untested cores No internal test access Mixed-signal devices PCB vs. SOC PCB SOC ELEC 7770: Advanced VLSI Design (Agrawal)

  5. SOC: Core-Based Design • Cores are predesigned and verified but untested blocks: • Soft core (synthesizable RTL) • Firm core (gate-level netlist) • Hard core (non-modifiable layout, often called legacy core) • Core is the intellectual property of vendor (internal details not available to user.) • Core-vendor supplied tests must be applied to embedded cores. ELEC 7770: Advanced VLSI Design (Agrawal)

  6. Partitioning for Test • Partition according to test methodology: • Logic blocks • Memory blocks • Analog blocks • Provide test access: • Boundary scan • Analog test bus • Provide test-wrappers (also called collars) for cores. ELEC 7770: Advanced VLSI Design (Agrawal)

  7. Test-Wrapper for a Core • Test-wrapper (or collar) is the logic added around a core to provide test access to the embedded core. • Test-wrapper provides: • For each core input terminal • A normal mode – Core terminal driven by host chip • An external test mode – Wrapper element observes core input terminal for interconnect test • An internal test mode – Wrapper element controls state of core input terminal for testing the logic inside core • For each core output terminal • A normal mode – Host chip driven by core terminal • An external test mode – Host chip is driven by wrapper element for interconnect test • An internal test mode – Wrapper element observes core outputs for core test ELEC 7770: Advanced VLSI Design (Agrawal)

  8. A Test-Wrapper Wrapper elements Core Functional core inputs Functional core outputs Scan chain Scan chain from/to External Test pins Scan chain Wrapper test controller to/from TAP ELEC 7770: Advanced VLSI Design (Agrawal)

  9. References • Test Wrapper: • B. Nadeau-Dosti, Design for At-Speed Test, Diagnosis and Measurement, Springer, 2000. • System Test: • R. Rajsuman, System-on-a-Chip: Design and Test, Artech-House, 2000. • M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits, Springer, 2000. ELEC 7770: Advanced VLSI Design (Agrawal)

  10. Overhead of Test Access • Test access is non-intrusive. • Hardware is added to each I/O signal of block to be tested. • Test access interconnects are mostly local. • Hardware overhead is proportional to: (Block area) – 1/2 ELEC 7770: Advanced VLSI Design (Agrawal)

  11. Overhead Estimate Rent’s rule: For a logic block the number of gates G and the number of terminals tare related by t = KGa where 1 ≤ K ≤ 5, anda ~ 0.5. Assume that block area A is proportional to G, i.e., t is proportional to A0.5. Since test logic is added to each terminal t, Test logic added to terminals Overhead = ──────────────────── ~ A–0.5 A ELEC 7770: Advanced VLSI Design (Agrawal)

  12. DFT Architecture for SOC Test source Test sink User defined test access mechanism (TAM) Func. outputs Functional outputs Functional inputs Func. inputs Module 1 Module N Test Test wrapper wrapper Instruction register control Test access port (TAP) Serial instruction data TDI SOC outputs SOC inputs TMS TCK TDO TRST ELEC 7770: Advanced VLSI Design (Agrawal)

  13. DFT Components • Test source: Provides test vectors via on-chip LFSR, counter, ROM, or off-chip ATE. • Test sink: Provides output verification using on-chip signature analyzer, or off-chip ATE. • Test access mechanism (TAM): User-defined test data communication structure; carries test signals from source to module, and module to sink; tests module interconnects via test-wrappers; TAM may contain bus, boundary-scan and analog test bus components. • Test controller: Boundary-scan test access port (TAP); receives control signals from outside; serially loads test instructions in test-wrappers. ELEC 7770: Advanced VLSI Design (Agrawal)

  14. Related Topics • IEEE 1500 standard • Core Test Language (CTL): • Test configuration(s) • Test interfaces • Test data (stimuli and responses) • Reference • Y. Zorian and A. Yessayan, “IEEE 1500 Utilization in SOC Design and Test,” Proc. International Test Conf., November 2005. • E. J. Marinissen, R. Kapur, M. Lousberg, T. McLaurin, M. Ricchetti, and Y. Zorian, “On IEEE P1500 Standard for Embedded Core Test,” J. Electronic Testing: Theory and Applications, vol. 18, no. 4-5, pp. 365-383, August 2002. ELEC 7770: Advanced VLSI Design (Agrawal)

  15. Summary • Functional test: verify system hardware, software, function and performance; pass/fail test with limited diagnosis; high ( ~100%) software coverage metrics; low ( ~70%) structural fault coverage. • Diagnostic test: High structural coverage; high diagnostic resolution; procedures use fault dictionary or diagnostic tree. • SOC design for testability: • Partition SOC into blocks of logic, memory and analog circuitry, often on architectural boundaries. • Provide external or built-in tests for blocks. • Provide test access via boundary scan and/or analog test bus. • Develop interconnect tests and system functional tests. • Develop diagnostic procedures. • Test scheduling to minimize test time and test power. ELEC 7770: Advanced VLSI Design (Agrawal)