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ELEC 7770 Advanced VLSI Design Spring 2007 Verification

ELEC 7770 Advanced VLSI Design Spring 2007 Verification. Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07. VLSI Realization Process. Customer’s need. Design.

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ELEC 7770 Advanced VLSI Design Spring 2007 Verification

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  1. ELEC 7770Advanced VLSI DesignSpring 2007Verification Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07 ELEC 7770: Advanced VLSI Design (Agrawal)

  2. VLSI Realization Process Customer’s need Design Determine requirements Write specifications Design synthesis and Verification Test development Fabrication Manufacturing test Manufacture Chips to customer ELEC 7770: Advanced VLSI Design (Agrawal)

  3. Verification and Testing Hardware design Manufacturing Specification Silicon Verification Testing 50-70% cost 30-50% cost ELEC 7770: Advanced VLSI Design (Agrawal)

  4. Definitions • Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. • Alternative Definition: Verification is a process used to demonstrate the functional correctness of a design. ELEC 7770: Advanced VLSI Design (Agrawal)

  5. What is Being Verified? • Given a set of specification, • Does the design do what was specified? RTL coding Specification Interpretation Verification J. Bergeron, Writing Testbenches: Functional Verification Of HDL Models, Springer, 2000. ELEC 7770: Advanced VLSI Design (Agrawal)

  6. Avoiding Interpretation Error • Use redundancy RTL coding Interpretation Specification Interpretation Verification ELEC 7770: Advanced VLSI Design (Agrawal)

  7. Methods of Verification • Simulation: Verify input-output behavior for selected cases. • Formal verification: Exhaustively verify input-output behavior: • Equivalence checking • Model checking • Symbolic simulation ELEC 7770: Advanced VLSI Design (Agrawal)

  8. Equivalence Checking • Logic equivalence: Two circuits implement identical Boolean function. • Logic and temporal equivalence: Two finite state machines have identical input-output behavior (machine equivalence). • Topological equivalence: Two netlists are identical (graph isomorphism). • Reference: S.-Y. Hwang and K.-T. Cheng, Formal Equivalence Checking and Design Debugging, Springer, 1998. ELEC 7770: Advanced VLSI Design (Agrawal)

  9. Compare Two Circuits • Graphs isomorphic? • Boolean functions identical? • Timing behaviors identical? a c b a c b f f ELEC 7770: Advanced VLSI Design (Agrawal)

  10. Model Checking • Construct an abstract model of the system, usually in the form of a finite-state machine (FSM). • Analytically prove that the model does not violate the properties (assertions) of original specification. • Reference: E. M. Clarke, Jr., O. Grumberg, and D. A. Peled, Model Checking, MIT Press, 1999. RTL coding Specification RTL Assertions Interpretation Model checking ELEC 7770: Advanced VLSI Design (Agrawal)

  11. Symbolic Simulation • Simulation with algebraic symbols rather than numerical values. • Self-consistency: A complex (more advanced) design produces the same result as a much simpler (and previously verified) design. • Reference: R. B. Jones, Symbolic Simulation Methods for Industrial Formal Verification, Springer, 2002. ELEC 7770: Advanced VLSI Design (Agrawal)

  12. Simulation: Testbench Testbench (HDL) Design under verification (HDL) ELEC 7770: Advanced VLSI Design (Agrawal)

  13. Testbench • HDL code: • Generates stimuli • Checks output responses • Approaches: • Blackbox • Whitebox • Greybox • Metrics (unreliable): • Statement coverage • Path coverage • Expression or branch coverage ELEC 7770: Advanced VLSI Design (Agrawal)

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