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ROD US ATLAS FDR, ROD Overview

ROD US ATLAS FDR, ROD Overview. Atlas Wisconsin Group Khang Dao, Damon Fasching, Douglas Ferguson, Owen Hayes, Richard Jared, John Joseph, Krista Marks, Mark Nagel Sriram Sivasubramaniyan (Oklahoma), Alden Stradling and Lukas Tomasek (Institute of Physics AV CR, Prague)

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ROD US ATLAS FDR, ROD Overview

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  1. ROD US ATLAS FDR, ROD Overview Atlas Wisconsin Group Khang Dao, Damon Fasching, Douglas Ferguson, Owen Hayes, Richard Jared, John Joseph, Krista Marks, Mark Nagel Sriram Sivasubramaniyan (Oklahoma), Alden Stradling and Lukas Tomasek (Institute of Physics AV CR, Prague) August 20, 2002

  2. ROD Overview

  3. ROD, TIM and BOC Overview TIM (Timing Interface Module) Receives clock and trigger information from the TTC Transmits clock and trigger information to the ROD Receives busy information from the ROD Masks and passes on busy to the L1 Trigger Operates stand alone under control of the RCC RCC (ROD Crate controller) Reads configuration data from the ATLAS data base Configures the TIM, ROD and BOC Controls the operation of the crate Monitors the crate during running Provides control and configuration in stand alone mode

  4. ROD, TIM and BOC Overview BOC (Back of Crate Card) (ROD optical fiber interface) Receives optical module data and formats data for the ROD input Receives module control data from ROD and formats data for the optical fibers Provides individual fiber delays Houses the Slink interface ROD (Read Out Driver) Formats input data Provides latency FIFOs Corrects header and trailer errors Corrects header and trailer Counts errors Provides for calibration of modules Traps and monitors event data Formats data for Slink input

  5. ROD Context

  6. Model #2 96Link ROD Event DataPath efbSTOPOUTPUT[0] 1b Link 0DATA 1b Formatter Fifo0 Event Fragment Builder Evnt Frg Bldr Fifo0 Router ROD Overview SLINK Event Fifo 32bx4W SLINK Events 32b Fifo 40b DATA Link 11DATA 1b DataValid 1b EvntFrgBldr DATA 46b Event DATA 46b XON/XOFF 1b from SLINK Link 12DATA 1b Formatter Fifo1 Fifo 40 DATA Link 23DATA 1b routerSTOPOUTPUT 1b DSP0 Fifo/Buffer DSP0 Module Processed 16b Trapped DATA Trapped 32b DATA Link 24DATA 1b Formatter Fifo2 Fifo 40b DATA Link 35DATA 1b DSP1 Fifo/Buffer DSP1 Module Processed 16b Trapped DATA Trapped 32b DATA Link 36DATA 1b Formatter Fifo3 Fifo 40b DATA Link 47DATA 1b DSP2 Fifo/Buffer DSP2 Module Processed 16b Trapped DATA Evnt Frg Bldr Fifo1 Trapped 32b DATA efbSTOPOUTPUT[1] 1b Link 48DATA 1b Formatter Fifo4 Fifo 40b DATA EvntFrgBldr DATA 46b DSP3 Fifo/Buffer DSP3 Module Link 59DATA 1b Processed 16b Trapped DATA Trapped 32b DATA Link 60DATA 1b Formatter Fifo5 Event 46b Header/Trailer Fifo 40b DATA Link 71DATA 1b RODController TIM EventDATA 16b bocCARD interface Link 72DATA 1b Formatter Fifo6 Fifo 40b DATA Link 83DATA 1b Link 84DATA 1b Formatter Fifo7 TIM TriggerDATA 8b from TIM Fifo 40b DATA Link 951DATA 1b vmeBUS DynamicMask 12b

  7. Model #2 96Link ROD DebugPath InMEM Memory0 Formatter Fifo0 Event Fragment Builder Evnt Frg Bldr Fifo0 Router Link 0DATA 1b Link 0DATA 1b SLINK Event Fifo 32bx4W SLINK Fifo 40b DATA Debug Memory0 Link 11DATA 1b Link 11DATA 1b Link 12DATA 1b Link 12DATA 1b Formatter Fifo1 Fifo 40 DATA Link 23DATA 1b Link 23DATA 1b DSP0 Fifo/Buffer DSP0 Module Link 24DATA 1b Link 24DATA 1b Formatter Fifo2 Fifo 40b DATA Link 35DATA 1b Link 35DATA 1b DSP1 Fifo/Buffer DSP1 Module Link 36DATA 1b Link 36DATA 1b Formatter Fifo3 Fifo 40b DATA Link 47DATA 1b Link 47DATA 1b DSP2 Fifo/Buffer DSP2 Module Evnt Frg Bldr Fifo1 Link 48DATA 1b Link 48DATA 1b Formatter Fifo4 InMEM Memory1 Debug Memory1 Fifo 40b DATA DSP3 Fifo/Buffer DSP3 Module Link 59DATA 1b Link 59DATA 1b Link 60DATA 1b Link 60DATA 1b Formatter Fifo5 Fifo 40b DATA Link 71DATA 1b Link 71DATA 1b RODController bocCARD interface Link 72DATA 1b Link 72DATA 1b Formatter Fifo6 Fifo 40b DATA Link 83DATA 1b Link 83DATA 1b Link 84DATA 1b Link 84DATA 1b Formatter Fifo7 Fifo 40b DATA vmeBUS EVNTMEM R/W & Control 32b Link 951DATA 1b Link 951DATA 1b DEBUGMEM R/W & Control 32b INMEM R/W & Control 34b

  8. ROD Overview Changes or major events since the last review 1. The formatter has been changed to increase the link to link latency from one to two clock tick. The resultant Formatter is more robust. The through rate is still determined by the the s-link. 2. The Router trapping of events for the DSP is more flexible. Based on event types with pre scale. 3. Controller FPGA code has been upgraded to have L1ID and BCID counter internal for self triggering of the ROD. 4. DSP software has been written to allow configuration and triggering of front end modules.

  9. ROD Overview Changes or major events since the last review 5. Four production model boards have been fabricated and debugged. So far they will be production RODs. 6. The number of back end DSPs loaded on the ROD has been changed from two to four. 7. DSP software has been written to allow histogramning of modules. (early version) 8. The data path has processed events at 100kHz. 9. Front end modules have been configure. 10. Event data has been readout over VME. 11. Histograms of calibration data has been made in the slave DSPs and read out over VME.

  10. ROD Overview VHDL Status FPGA Utilization VHDL Simulation Formatter SCT 81% 100% Complete Event Fragment Builder 71% 100% Complete Router 48% 100% Complete ROD Resource Interface 78% 100% Complete Program Manger 54% 100% Complete Other Status Layout of the PC is being completed Simulation of symbols on schematic has been completed Board level simulation of the data path is complete

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