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Instruction Level Parallelism: Loop Level Parallelism. Pipelining and Exploiting Instruction-Level Parallelism (ILP). Pipelining increases performance by overlapping the execution of independent instructions. The CPI of a real-life pipeline is given by:
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Pipelining and Exploiting Instruction-Level Parallelism (ILP) • Pipelining increases performance by overlapping the execution of independent instructions. • The CPI of a real-life pipeline is given by: Pipeline CPI = Ideal Pipeline CPI + Structural Stalls + RAW Stalls + WAR Stalls + WAW Stalls + Control Stalls • A basic instruction block is a straight-line code sequence with no branches in, except at the entry point, and no branches out except at the exit point of the sequence . • The amount of parallelism in a basic block is limited by instruction dependence present and size of the basic block. • In a typical integer code, dynamic branch frequency is about 15% (average basic block size of 7 instructions).
Increasing Instruction-Level Parallelism • A common way to increase parallelism among instructions is to exploit parallelism among iterations of a loop • (i.e Loop Level Parallelism, LLP). • This is accomplished by unrolling the loop either statically by the compiler, or dynamically by hardware, which increases the size of the basic block present. • In this loop every iteration can overlap with any other iteration. Overlap within each iteration is minimal. for (i=1; i<=1000; i=i+1;) x[i] = x[i] + y[i];
MIPS Loop Unrolling Example • For the loop: for (i=1; i<=1000; i++) x(i) = x(i) + s;; The straightforward MIPS assembly code is given by: Loop: L.D F0, 0 (R1) ;F0=array element ADD.D F4, F0, F2 ;add scalar in F2 S.D F4, 0(R1) ;store result SUBI R1, R1, # 8 ;decrement pointer 8 bytes BNE R1,Loop ; branch R1!=zero R1 is initially the address of the element with highest address.
FP Loop: Where are the Hazards? Loop: LD F0,0(R1) ;F0=vector element ADDD F4,F0,F2 ;add scalar from F2 SD 0(R1),F4 ;store result SUBI R1,R1,8 ;decrement pointer 8B (DW) BNEZ R1,Loop ;branch R1!=zero Instruction Instruction Latency inproducing result using result clock cycles FP ALU op Another FP ALU op 3 FP ALU op Store double 2 Load double FP ALU op 1 Load double Store double 0 Integer op Integer op 0 • Where are the stalls?
FP Loop Showing Stalls • 9 clock cycles per loop iteration. • Rewrite code to minimize stalls? 1 Loop: LD F0,0(R1) ;F0=vector element 2 stall;stall one cycle between LD and FP ALU op 3 ADDD F4,F0,F2 ;add scalar in F2 4 stall;stall two cycles between FP ALU op and SD 5 stall 6 SD 0(R1),F4 ;store result 7 SUBI R1,R1,8 ;decrement pointer 8B (DW) 8 BNEZ R1,Loop ;branch R1!=zero 9 stall ;delayed branch slot
Revised FP Loop Minimizing Stalls • Code now takes 6 clock cycles per loop iteration • Speedup = 9/6 = 1.5 • Unroll loop 4 times to make faster? 1Loop: LD F0,0(R1) 2 stall 3 ADDD F4,F0,F2 4 SUBI R1,R1,8 5 BNEZ R1,Loop ;delayed branch 6 SD 8(R1),F4;altered when move past SUBI Swap BNEZ and SD by changing address of SD
Unroll Loop Four Times (straightforward way) Rewrite loop to minimize stalls? • 1 Loop: LD F0,0(R1) • 2 ADDD F4,F0,F2 • 3 SD 0(R1),F4 ;drop SUBI & BNEZ • 4 LD F6,-8(R1) • 5 ADDD F8,F6,F2 • 6 SD -8(R1),F8 ;drop SUBI & BNEZ • 7 LD F10,-16(R1) • 8 ADDD F12,F10,F2 • 9 SD -16(R1),F12 ;drop SUBI & BNEZ • 10 LD F14,-24(R1) • 11 ADDD F16,F14,F2 • 12 SD -24(R1),F16 • 13 SUBI R1,R1,#32 ;alter to 4*8 • 14 BNEZ R1,LOOP • 15 stall • 15 + 4 x (2 + 1)= 27 clock cycles, or 6.8 cycles per iteration (2 stalls for SD and 1 stall for LD)
Unrolled Loop That Minimizes Stalls • What assumptions made when moved code? • OK to move store past SUBI even though SUBI changes register • OK to move loads before stores: get right data? • When is it safe for compiler to make such changes? • 1 Loop: LD F0,0(R1) • 2 LD F6,-8(R1) • 3 LD F10,-16(R1) • 4 LD F14,-24(R1) • 5 ADDD F4,F0,F2 • 6 ADDD F8,F6,F2 • 7 ADDD F12,F10,F2 • 8 ADDD F16,F14,F2 • 9 SD 0(R1),F4 • SD -8(R1),F8 • SD -16(R1),F8 • 13 SUBI R1,R1,#32 • 12 BNEZ R1,LOOP • 14 SD 8(R1),F16 ;8-32 = -24 • 14 clock cycles or 3.5 clock cycles per iteration
Summary of Loop Unrolling Example • Determine that it was legal to move the SD after the SUBI and BNEZ, and find the amount to adjust the SD offset. • Determine that unrolling the loop would be useful by finding that the loop iterations are independent, except for the loop maintenance code. • Use extra registers to avoid unnecessary constraints that would be forced by using the same registers for different computations.
Summary of Loop Unrolling Example • Eliminate the extra tests and branches and adjust the loop maintenance code. • Determine that the loads and stores in the unrolled loop can be interchanged by observing that the loads and stores from different iterations are independent. This requires analyzing the memory addresses and finding that they do not refer to the same address. • Schedule the code, preserving any dependences needed to yield the same result as the original code.
Loop-Level Parallelism (LLP) Analysis • Loop-Level Parallelism (LLP) analysis focuses on whether data accesses in later iterations of a loop are data dependent on data values produced in earlier iterations. e.g. in for (i=1; i<=1000; i++) x[i] = x[i] + s; the computation in each iteration is independent of the previous iterations and the loop is thus parallel. The use of X[i] twice is within a single iteration. • Thus loop iterations are parallel (or independent from each other). • Loop-carried Dependence: A data dependence between different loop iterations (data produced in earlier iteration used in a later one) – limits parallelism. • Instruction level parallelism (ILP) analysis, on the other hand, is usually done when instructions are generated by the compiler.
LLP Analysis Example 1 • In the loop: for (i=1; i<=100; i=i+1) { A[i+1] = A[i] + C[i]; /* S1 */ B[i+1] = B[i] + A[i+1];} /* S2 */ } (Where A, B, C are distinct non-overlapping arrays) • S2 uses the value A[i+1], computed by S1 in the same iteration. This data dependence is within the same iteration (not a loop-carried dependence). • does not prevent loop iteration parallelism. • S1 uses a value computed by S1 in an earlier iteration, since iteration i computes A[i+1] read in iteration i+1 (loop-carried dependence, prevents parallelism). The same applies for S2 for B[i] and B[i+1] • These two dependences are loop-carried spanning more than one iteration preventing loop parallelism.
LLP Analysis Example 2 • In the loop: for (i=1; i<=100; i=i+1) { A[i] = A[i] + B[i]; /* S1 */ B[i+1] = C[i] + D[i]; /* S2 */ } • S1 uses the value B[i] computed by S2 in the previous iteration (loop-carried dependence) • This dependence is not circular: • S1 depends on S2 but S2 does not depend on S1. • Can be made parallel by replacing the code with the following: A[1] = A[1] + B[1]; for (i=1; i<=99; i=i+1) { B[i+1] = C[i] + D[i]; A[i+1] = A[i+1] + B[i+1]; } B[101] = C[100] + D[100]; Loop Start-up code Loop Completion code
A[1] = A[1] + B[1]; B[2] = C[1] + D[1]; A[99] = A[99] + B[99]; B[100] = C[99] + D[99]; A[2] = A[2] + B[2]; B[3] = C[2] + D[2]; A[100] = A[100] + B[100]; B[101] = C[100] + D[100]; LLP Analysis Example 2 for (i=1; i<=100; i=i+1) { A[i] = A[i] + B[i]; /* S1 */ B[i+1] = C[i] + D[i]; /* S2 */ } Original Loop: Iteration 99 Iteration 100 Iteration 1 Iteration 2 . . . . . . . . . . . . Loop-carried Dependence • A[1] = A[1] + B[1]; • for (i=1; i<=99; i=i+1) { • B[i+1] = C[i] + D[i]; • A[i+1] = A[i+1] + B[i+1]; • } • B[101] = C[100] + D[100]; Modified Parallel Loop: Iteration 98 Iteration 99 . . . . Iteration 1 Loop Start-up code A[1] = A[1] + B[1]; B[2] = C[1] + D[1]; A[99] = A[99] + B[99]; B[100] = C[99] + D[99]; A[2] = A[2] + B[2]; B[3] = C[2] + D[2]; A[100] = A[100] + B[100]; B[101] = C[100] + D[100]; Not Loop Carried Dependence Loop Completion code
