ENG2410 Digital Design: Week #10 “Sequencing and Control Examples”

1. ENG2410Digital Design: Week #10“Sequencing and ControlExamples” S. Areibi School of Engineering University of Guelph

2. Traffic Light Controller

3. Example (Traffic Light Controller) • Find an ASM chart for a traffic light controller that works as follows: • A timing signal T is the input to the controller • T defines the yellow light as well as the changes of RED and GREEN lights • While T = 0, the green light is on for one signal, the red light is on for other signal • While T = 1, the yellow light is on for the signal that was previously green and the signal that was previously red remains red • When T becomes 0, the signal that was previously yellow becomes RED and the signal that was previously RED becomes GREEN • This pattern continues

4. Example (Traffic Light Controller) • While T = 0, the green light is on for one signal, the red light is on for other signal • While T = 1, the yellow light is on for the signal that was previously green and the signal that was previously red remains red • When T becomes 0, the signal that was previously yellow becomes RED and the signal that was previously RED becomes GREEN • This pattern continues

5. ASM for Traffic Light Controller GREEN RED YELLOW RED RED GREEN RED YELLOW 0 1 1 0 0 1 1 0 T T T T Implement using One Flip Flop Per State Implement using Sequence Register and Decoder

6. Serial Multiplier

7. Multiplier Example • Example: (101 x 011) Base 2 • Note that the partial productsummation for n digits, base 2 numbers requires adding up to n digits (with carries) in a column. • Note also nx m digit multiplygenerates up to an m + ndigit result (same as decimal). Partial products are: 101 x 0, 101 x 1, and 101 x 1

8. Example (1 0 1) x (0 1 1) Again Reorganizing example to follow hardware algorithm: Multiplier: Register Q Multiplicand: Register B Scratchpad: Register A Clear C || A Multipler0 = 1 => Add B Addition Shift Right (Zero-fill C) Multipler1 = 1 => Add B Addition Shift Right Multipler2 = 0 => No Add, Shift Right Clear C || A

9. Hardware ? (Data Path + Control) • A Parallel Adder • Switches to enter Multiplier/Multiplicand • Shift Register Q (Multiplier) • Register B (Multiplicand) • Counter (to know when to stop) • Zero detection circuit (input to control) • Shift Register A (scratch pad) • Flip Flop to store Carry of Adder • Detect when Q0 is zero or one (input to control) • A Go signal to start (input to control) • Control Output? • Load, Load_B, Clear_C, Initialize_A, Shift

10. Multiplier Datapath: Block Diagram IN n 1 2 n Multiplicand Counter P Register B n log n 2 Zero detect G (Go) Parallel adder C out Z n n Multiplier Q Control o unit 0 C Shift register A Shift register Q 4 n Product Control signals OUT

11. Multiplier Example: Required Steps • The multiplicand (top operand) is loaded into register B (X) • The multiplier (bottom operand) is loaded into register Q (X) • Register C|| A is initialized to 0 when G becomes 1. • The partial products are formed in register C||A||Q. • Each multiplier bit, beginning with the LSB, is processed (if bit is 1, use adder to add B to partial product; if bit is 0, do nothing) • C||A||Q is shifted right using the shift register • Partial product bits fill vacant locations in Q as multiplier is shifted out • If overflow during addition, the outgoing carry is recovered from C during the right shift • Steps 5 and 6 are repeated until Counter P = 0 as detected by Zero detect. • Counter P is initialized in step 4 to n – 1, n = number of bits in multiplier

12. Multiplier Example: Block Diagram IN n 1 2 • The multiplicand (top operand) is loaded into register B(X) • The multiplier (bottom operand) is loaded into register Q(X) n Multiplicand Counter P Register B n log n 2 Zero detect G (Go) Parallel adder C out Z n n Multiplier Q Control o unit 0 C Shift register A Shift register Q 4 n Product Control signals OUT

13. Multiplier Example: Block Diagram IN n 1 • Register C||A is initialized to 0 when G becomes 1. • The partial products are formed in register C||A||Q 2 n Multiplicand Counter P Register B n log n 2 Zero detect G (Go) Parallel adder C out Z n n Multiplier Q Control o unit 0 C Shift register A Shift register Q 4 n Product Control signals OUT

14. Multiplier Example: Block Diagram • Each multiplier bit, beginning with the LSB, is processed • if bit is 1, use adder to add B to partial product; • if bit is 0, do nothing IN n 1 2 n Multiplicand Counter P Register B n log n 2 Zero detect G (Go) Parallel adder C out Z n n Multiplier Q Control o unit 0 C Shift register A Shift register Q 4 n Product Control signals OUT

15. Multiplier Example: Block Diagram • C||A||Q is shifted right using the shift register • Partial product bits fill vacant locations in Q as multiplier is shifted out • If overflow during addition, the outgoing carry is recovered from C during the right shift IN n 1 2 n Multiplicand Counter P Register B n log n 2 Zero detect G (Go) Parallel adder C out Z n n Multiplier Q Control o unit 0 C Shift register A Shift register Q 4 n Product Control signals OUT

16. Multiplier Example: Block Diagram • Steps (5 and 6) are repeated until Counter P = 0 as detected by Zero detect. • Counter P is initialized in step 4 to n – 1, n = number of bits in multiplier IN n 1 2 n Multiplicand Counter P Register B n log n 2 Zero detect G (Go) Parallel adder C out Z n n Multiplier Q Control o unit 0 C Shift register A Shift register Q 4 n Product Control signals OUT

17. Multiplier Example: ASM Chart (continued) Three states are employed using a Mealy output model: • IDLE - state in which: • input G is used as the condition for starting the multiplication, and • C, A, and P are initialized • MUL0 - state in which conditional addition is performed based on the value of Q0. • MUL1 - state in which: • right shift is performed to capture the partial product and position the next bit of the multiplier in Q0 • the terminal count of 0 for down counter P is used to sense completion or continuation of the multiply.

18. Multiplier Example: ASM Chart IDLE MUL0 0 1 G 0 1 Q 0 Three states are employed using a Mealy output model: • IDLE - state in which: • input G is used as the condition for starting the multiplication, and • C, A, and P are initialized • MUL0 - state in which conditional addition is performed based on the value of Q0. • MUL1 - state in which: • right shift is performed to capture the partial product and position the next bit of the multiplier in Q0 • the terminal count of 0 for down counter P is used to sense completion or continuation of the multiply. C ← 0, A ← 0 P ← n – 1 A ← A + B, C ← C out MUL1 C ← 0, C || A || Q ← sr C || A || Q, 1 P ← P – 0 1 Z

19. Multiplier Example: Control Unit • In implementing a complex control unit, designers usually have to deal with (separate) two distinct aspects • The generation of the control signals • Sequencing of the operations (what will happen next) • We can separate the two aspects by dividing the original ASM specification into two parts: • A table that defines the control signals in terms of states and inputs • A simplified ASM chart that represents only transitions from state to state

20. Multiplier Example: Control Signal Table Bloc k Dia g ram Mod u l e Register A : Register B : F lip-F lop C Register Q Cou n ter P :

21. Multiplier Example: Control Signal Table Bloc k Dia g ram Mod u l e Mi cr oo pe ra ti on ← Register A : A 0 A ← A + B ← C || A || Q sr C || A || Q Register B : B ← IN F lip-F lop C : C← 0 C ← C ou t Register Q : Q ← IN ← C || A || Q sr C || A || Q – Cou n ter P : P ← n 1 ← – P P 1

22. Multiplier Example: Control Signal Table Bloc k Dia g ram Contr o l Mod u l e Mi cr oo pe ra ti on Si gn al N a me ← Register A : A 0 I nitia liz e A ← A + B Load ← C || A || Q sr C || A || Q Shift_dec Register B : B ← IN Load_B F lip-F lop C : C← 0 C lea r _C C ← C Load ou t Register Q : Q ← IN Load_Q ← C || A || Q sr C || A || Q Shift_dec – Cou n ter P : P ← n 1 I nitia liz e ← – P P 1 Shift_dec

23. Multiplier Example: ASM Chart IDLE MUL0 0 1 G 0 1 Q 0 C ← 0, A ← 0 P ← n – 1 A ← A + B, C ← C out MUL1 C ← 0, C || A || Q ← sr C || A || Q, 1 P ← P – 0 1 Z

24. Multiplier Example: Control Signal Table Bloc k Dia g ram Contr o l Contr o l Mod u l e Mi cr oo pe ra ti on Si gn al N a me Exp r e ssi on ← IDLE · Register A : A 0 I nitia liz e G

25. Multiplier Example: ASM Chart IDLE MUL0 0 1 G 0 1 Q 0 C ← 0, A ← 0 P ← n – 1 A ← A + B, C ← C out MUL1 C ← 0, C || A || Q ← sr C || A || Q, 1 P ← P – 0 1 Z

26. Multiplier Example: Control Signal Table Bloc k Dia g ram Contr o l Contr o l Mod u l e Mi cr oo pe ra ti on Si gn al N a me Exp r e ssi on ← IDLE · Register A : A 0 I nitia liz e G A ← A + B Load MUL0 · Q0

27. Multiplier Example: ASM Chart IDLE MUL0 0 1 G 0 1 Q 0 C ← 0, A ← 0 P ← n – 1 A ← A + B, C ← C out MUL1 C ← 0, C || A || Q ← sr C || A || Q, 1 P ← P – 0 1 Z

28. Multiplier Example: Control Signal Table Bloc k Dia g ram Contr o l Contr o l Mod u l e Mi cr oo pe ra ti on Si gn al N a me Exp r e ssi on ← IDLE · Register A : A 0 I nitia liz e G A ← A + B Load MUL0 · Q0 ← C || A || Q sr C || A || Q Shift_dec M UL1

29. Multiplier Example: Control Signal Table Bloc k Dia g ram Contr o l Contr o l Mod u l e Mi cr oo pe ra ti on Si gn al N a me Exp r e ssi on ← IDLE · Register A : A 0 I nitia liz e G A ← A + B Load MUL0 · Q0 ← C || A || Q sr C || A || Q Shift_dec M UL1 Register B : B ← IN Load_B LO ADB F lip-F lop C : C← 0 C lea r _C IDLE · G + MUL1 C ← C Load — ou t Register Q : Q ← IN Load_Q LO ADQ ← C || A || Q sr C || A || Q Shift_dec — – Cou n ter P : P ← n 1 I nitia liz e — ← – P P 1 Shift_dec —

30. Multiplier Example: Control Table (continued) • Signals are defined on a register basis • LOADQ and LOADB are external signals controlled from the system using the multiplier and will not be considered a part of this design • Note that many of the control signals are “reused” for different registers. • These control signals are the “outputs” of the control unit • With the outputs represented by the table, they can be removed from the ASM giving an ASM that represents only the sequencing (next state) behavior

31. Multiplier Example: ASM Chart IDLE MUL0 0 1 G 0 1 Q 0 C ← 0, A ← 0 P ← n – 1 A ← A + B, C ← C out MUL1 C ← 0, C || A || Q ← sr C || A || Q, 1 P ← P – 0 1 Z

32. Example - Sequencing Part of ASM IDLE 00 1 0 G MUL0 01 MUL1 10 0 1 Z

33. Multiplier Control Unit Implementation

34. 2 DEMUX D EN 0 D A 1 0 Multiplier: One Flip-flop per State Design 4 5 START Initialize IDLE 1 D 4 5 C Clear _C 2 MUL0 Q 1 0 DEMUX Load D D EN 0 G A D C 0 1 MUL1 1 5 00 IDLE D Shift_dec Clock C 0 1 G 01 MUL0 Z 10 MUL1 0 1 Z

35. Multiplier: One Flip-flop per State Design

36. Example: Cont .. Sequence Register and Decoder Design • First, define: • States: IDLE, MUL0, MUL1 • Input Signals: G, Z, Q0 (Q0 affects outputs, not next state) • Output Signals: Initialize, LOAD, Shift_Dec, Clear_C • State Transition Diagram • Output Function. • Second, find • State Assignments (two bits required) • We will use two state bits to encodethe three state IDLE, MUL0, and MUL1.

37. Example: Cont .. Sequence Register and Decoder Design Assuming that state variables M1 and M0 are decoded into states, the next state part of the state table is:

38. Example: Cont .. Sequence Register and Decoder Design

39. Example: Cont .. Sequence Register and Decoder Design • Finding the equations for M1 and M0 is easier due to the decoded states: M1 = MUL0 M0 = IDLE · G + MUL1 · Z’ • Note that since there are five variables, a K-map is harder to use, so we have directly written reduced equations. • The output equations using the decoded states:Initialize = IDLE · G Load = MUL0 · Q0Clear_C = IDLE · G + MUL1Shift_dec = MUL1

40. Sequencer and Decoder Design START Initialize G M 0 D Clear_C Z C DECODER IDLE A0 0 MUL0 1 MUL1 Shift_dec 2 A1 3 M 1 D C Load Q 0

41. Multiplier Microprogrammed Control

42. Problems With HardWired Designs • Sequencing & micro-operation logic gets complex • Difficult to design, prototype, and test • Resultant design is inflexible, and difficult to build upon (Pipeline, multiple computation units, etc.) • Adding new instructions requires major design and adds complexity quickly

43. Micro-programmed Control • Use sequences of instructionsto control complex operations • An alternative to a hardwired control unit • Called micro-programming, microcode, or firmware

44. Microprogrammed Control

45. Micro-Programmed Control • A control unit with its binary control values stored as words in memory is called a micro-programmed control. • Each word in the control memory contains a microinstruction that specifies one or more micro-operations for the system. • A sequence of microinstructions constitutes a microprogram. • A micro-program is often fixed at the time of the system design and so is usually stored in ROM. • A micro-program can also be written in RAM but has to be loaded initially at system startup. 00101010101100 01110001110000 00000000100000 microinstruction 00011111110000 00001111111111 0010101010101011111111000000 microprogram 0101010101010100000000000001 11111111111111 Memory

46. ASM Chart  Microprogrammed Control microinstruction 00101010101100 01110001110000 00000000100000 00011111110000 00001111111111 0010101010101011111111000000 microprogram 0101010101010100000000000001 11111111111111 Memory

47. Microprogrammed Control Organization Control Memory »A memory is part of a control unit : »Computer Memory (employs a microprogrammed control unit) • Main Memory : for storing user program (Machine instruction/data) • Control Memory : for storing microprogram (Microinstruction) Data Path ALU + RegFile PC Control Unit IR Main Memory LDA .. SUB .. Microinstructions ………………………… ……………………….. ………………………… Sequencer (Next Address Gen)

48. Machine Instruction vs Microinstruction Format

49. A Micro-Programmed Control Unit Organization • The microinstruction is stored in the Control Memory (ROM). • Control Address Register (CAR) specifies the address of the microinstruction. • The Control Data Register (CDR) may hold the instruction currently being executed. • The next address generator produces the next address (Sequencer).

50. A Micro-Programmed Control Unit Organization • One of the functions of the control word is to determine the address of the next microinstruction to be executed. • This microinstruction may be the next one in sequence • Or may be located somewhere else in the control memory • Therefore, one or more bits that specify how to determine the address of the next microinstruction must be present in the current microinstruction. • The next address may also be a function of status and external control inputs.