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WP7& 8 Progress Report

WP7& 8 Progress Report. ITS Plenary meeting, 23 April 2014 LG, PK, VM, JR. Objectives 2014 and current status. ITS objectives for 2014 – WP7 and WP8 Finalization of OB geometry (with inputs from WP1 and WP2) and layout (with WP9 and WP10). Power Bus. Flexible Printed Circuit. Half-Stave.

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WP7& 8 Progress Report

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  1. WP7&8 Progress Report ITS Plenary meeting, 23 April 2014 LG, PK, VM, JR Objectives 2014 and current status

  2. ITS objectives for 2014 – WP7 and WP8 Finalization of OB geometry (with inputs from WP1 and WP2) and layout (with WP9 and WP10). Power Bus Flexible Printed Circuit Half-Stave 2 x 7 Pixel Chips Half-Stave Cold Plate Half-Stave Left Half-Stave Right Space Frame WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  3. FPC extender • Study of the end of Stave services has started WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  4. Cover-sheet 25 µm Copper 18µm Kapton75 µm Copper 18µm ITS objectives for 2014 – WP7 and WP8 Design, prototype and characterization of FPC • Layout specs: • Size: 32.1 mm x 216 mm • Plated holes (~200 μm diameter) • Pads for FPC to FPC and FPC to PB interconnections test • tin soldering  short cables or SMD 0402 resistors, metallized holes • stack-up WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  5. TDR-layout prototype • Daisy-chain layout prototype • Similar to the IB • Delivery ongoing • To be used for soldering tests 30,1 mm 30,1 mm 210,6 mm 220,4 mm WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  6. Functioning layout prototype • Main features • 2 x Master chips • Parallel data transmission • Internal daisy chain: • 4 data lines @ 80Mb/s (pins DATAIN[3:0] - DATAOUT[3:0]) • 1 Clear To Send line (pins CTSO-CTSI) • internal CLK and CRTL (pins CLK – CTRL): • busy signal • Differential CLK and CTRL (DCLKI – DCTRLI) • from end-stave -> to each Master (traces on the 1 mm off the chips) • 6 by-passing differential DATA lines from adjacent modules • Module and chip Identification • Geometry and Layout • Differential lines: • width = 100μm, spacing = 100μm, pitch between adjacent pairs = 300μm • Pads for FPC to FPC and FPC to PB connection • size to be defined WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  7. Chip Floorplan v2 (by Gianluca) OB FPC WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  8. Functioning FPC routing WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  9. ITS objectives for 2014 – WP7 and WP8 Design, prototype and characterization of Power Bus • Baseline for the prototype development: • Al conductive layers • Double layers: 2 x 100 μm • Length: 180 cm (including 30 cm extension) • Parallel rails • Metalized holes for FPC connection • Connectors? • Investigations ongoing with: • CISEL (Castelfidardo, Italy) • Industrial producer of Cu flat cables • Interest to develop the technology for Al-based long flat cables • Plating holes in-house or in outsourcing • Plans: production of ~10 samples, estimated time 4 to 8 weeks (in house/outside) • Laser cut: accuracy 100-200um • PH-DT-DD (PCB workshop, contact: Rui de Oliveira) • Design of test boards and PB dummy prototypes finalized • Offer received today: 5um Al / 50um kapton+glue/ 25um Al Holes are not plated - No finishing and no solder mask • Test board: 250 CHF - Long cable: 2900 CHF for 10 pieces (min) WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  10. ITS objectives for 2014 – WP7 and WP8 Development of HIC assembly and test procedure and set-up (with WP4 and WP6) • Semi-manual assembly procedure well advanced • Handling and alignment: dies 50 μm thin and 15 x 30 mm2 large • Handling and alignment of FPC • Shipping of HICs to the Stave construction centers under test • Glued dummy HICs: • Several samples already produced • Chip position accuracy better than 5 μm • Flatness quite good, to be verified with final components and soldering • They are being used for the Stave assembly studies • Soldered dummy HIC: • Laser soldering of pre-glued single assemblies (back-up option) • Laser soldering of a whole dummy HIC  end of May • Dedicated jigs, compatible with the laser set-up, are being manufactured WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  11. Semi-manualAssembly Procedure WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  12. GlueddummyHICs • Last batch: • 10 samples without carbon plate for the studies of the Stave assembly • 8 modules ready • 2 modules to be completed by end of April WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  13. HICs shipping HIC Alignment station dummy HIC HIC box references holes for HIC box Pins for HICpre-alignment Conductive carrying case for housing the 7-HICs shipping plate 1 3 4 5 2 7 6 foam 7-HICs shipping plate WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  14. Soldering of pre-glued single assemblies • 2 pad chips glued to single-die FPCs 4 gluing dots glue: Eccobond 45 diameter: 600 µm thickness: 40 µm Chip on the back side • Single chips soldered assemblies Electrical daisy-chain test of 50 contacts WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  15. Jigs for HIC soldering 2 1 Reference pins 3 4 WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  16. ITS objectives for 2014 – WP7 and WP8 Development of prototype of OB staves based on “pad chips”, dimensional survey and characterization (mechanical and thermal) (joint project with WP9) • Development of the Half-stave and Stave assembly procedure • Alignment and gluing of HICs on the Coldplateongoing • Topic talk by Stefania • Milestones • Coldplate equipped with dummy HICs and PB  July 2014 • Following milestones • Dummy Stave  beginning of 2015 • Functional Half-stave  Spring 2015 WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  17. ITS objectives for 2014 – WP7 and WP8 • Development and characterization of HIC and Module (Stave?) based on • Full-Scale Pixel Chips. • HIC-board prototype with 14 full-scale pixel chips to study system aspects • Topic talk by Paul • Milestones • HIC-board prototype with 14 full-scale pixel chips July 2014 • HIC prototype with Cu-FPC and 14 available full-scale pixel chips   December 2014 WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  18. ITS objectives for 2014 – WP7 and WP8 • Document on dimensional and position survey procedure (joint with WP6 and WP9) • Not yet started WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

  19. Summary • Objectives for 2014 are on track • The study of few key system aspects should be started as soon as possible • Power distribution • Interconnections • ... WP7&8 Progress Report ITS Plenary Meeting, 23/04/2014

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