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Smart Technologies for Effective Reconfiguration: The FASTER approach

Smart Technologies for Effective Reconfiguration: The FASTER approach. July 10 th 2012 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip York, UK.

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Smart Technologies for Effective Reconfiguration: The FASTER approach

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  1. Smart Technologies for Effective Reconfiguration:The FASTER approach July 10th 20127th International Workshop on Reconfigurable Communication-centric Systems-on-ChipYork, UK M. D. Santambrogio, D. Pnevmatikatos, K. Papadimitriou, C. Pilato, G. Gaydadjiev, D. Stroobandt, T. Davidson, T. Becker, T. Todman, W. Luk, A. Bonetto, A. Cazzaniga, G. C. Durelli, D. Sciuto

  2. Reconfiguration The process of physically altering the location or functionality of network or system elements. Automatic configuration describes the way sophisticated networks can readjust themselves in the event of a link or device failing, enabling the network to continue operation. Gerald Estrin, 1960 2

  3. Reconfigurable Technology • Technology for adaptable hardware systems • Can add/removecomponentsatrun-time/productlifetime • Flexibilityat hardware speed (notquite ASIC) • Parallelismat hardware level (depending on application) • Ideally: alter function & interconnection of blocks • Implementation in: • FPGAs: fine grain, complex gate plus memory and DSP blocks • CoarseGrain (custom) chips: multiple ALUs, multiple (simple) programmable processing blocks, etc.

  4. An issue as a new opportunity • Programming has become very difficult • Impossible to balance all constraints manually • More computational horse-power than ever before • Cores are free, reconfigurable logic available on chip, cores can be heterogeneous • Energy is new constraint • Software must become energy and space aware • Modern computing systems need to be flexible and adaptive • To optimize and meet their requirements taking advantage as much as possible of the underlying complex heterogeneous architectures

  5. FASTER participants

  6. FASTER Motivation • Focus on fine-grainreconfiguration (not-limited) • Creatingreconfigurablesystemsisnotstraightforward! • The designer has to: • Identifyportions to be reconfigured • Establish a schedule that (a) respectsdependencies (b) achieves performance and otherconstraints • Manage the systemresources (reconfiguration area mainly) • Reconfigurationcostissubstantial (use wisely) • Verify a changingsystem! • Toolsupport for thesetasksisstillquitebasic • Resource management is up to the user • Verification: anysupporttoday?

  7. FASTER Goals and Innovation • Include reconfigurabilityas an explicit design concept in computingsystems design, along with methods and toolsthatsupportrun-time reconfiguration in the entire design methodology • Provide a framework for analysis, synthesis and verification of a reconfigurablesystem • Provideefficient and transparentruntimesupport for partial and dynamicreconfiguration, including micro-reconfiguration • Demonstrateusability & performance on commercial applications (Maxeler, ST Microelectronics, Synelixis)

  8. FASTER: Overall Methodology

  9. High-level Analysis & Reconfigurable System Definition (led by PDM) • Analyze each application and: • Define its components • HW/SW, reconfigurable HW modules, … • Estimate, identify, and optimize its performance and constraints on the target reconfigurable computing system • Execution time, floorplanning and placement, HW/SW execution, … • How to achieve these goals?

  10. How to achieve these goals? • by Identifying: • The partitioning of the input specification in HW/SW components • The implementation(s) of the modules to be realized as HW accelerators • The corresponding level of reconfigurability for HW components • none, micro, region based • The power constraints • The floorplanning constraints • size and shape • The placement requirements • The baseline schedule for application’s execution

  11. A bird’s eye view on the design phase

  12. Micro-reconfiguration (led by Gent) • In some applications we can identify fast changing inputs vs. slow‐changing  “parameters” • Parameters trigger a small-scale reconfiguration • We want to: • Identify parameters • Create bitfile with “holes” • Parameter values => reconfiguration bits for missing “holes” • Fine grain, faster reconfiguration time! • Extend the idea from logic (TLUT) to wires (TCON)

  13. Micro-reconfiguration (led by Gent)

  14. Verifying Reconfigurable Systems (led by Imperial) • Study design validation approaches: simulation, emulation and formal verification • Extend symbolic simulation to dynamic aspects of reconfigurable design • In some cases static approaches may not be able to verify the entire RC system • We will use run‐time verification. Address and minimize impact on: • Speed, area and power • Light‐weight architectural support

  15. Run-time System (Chalmers/FORTH) • Providesupport for partial & dynamicreconfiguration • Extend the OS capabilities, integrate in existingsystems • Efficient on-line scheduling and placement of task modules • Evaluatereconfigurationoverhead • Propose advancedmechanisms to support • Scheduling • Relocation • Fragmentation = f(relocation, scheduling) • Area allocation • Bottom-line: Extent the flexibility of run-time support

  16. FASTER Runtime System Area allocation Scheduling Improve: -Speed -Power -Temperature Placement Fragmentation Routing Relocation Prefetching

  17. Design phase and runtime support • Define a reconfigurable design methodologythat exploits FPGAs: • Design automation flow and tools to generate hardware and software components and runtimesupport • Dynamicallyreconfigurable hardware and software architectures • Runtime swap of reconfigurablecores • Exploit dynamicreconfigurability for different target reconfigurablearchitectures. • Define and implement a new generation of self reconfigurablearchitecturesbased on Linux • Increase the reconfiguration performance via noveltechniques, i.e. runtimereconfigurablecoresrelocation, reconfigurablecoresidentification, reconfigurablecoresreuse

  18. Runtime Reconfiguration Management • Reconfigurable architecture • Static Area: used to control the reconfiguration process • Reconfigurable Area: used to swap at runtime different cores • Reconfiguration- oriented communication infrastructure • Runtime reconfiguration managed via SW (slide 21) • Standalone, Operating System • Increased portability of user applications • Inherited multitasking capabilities • Simplified software development process • Bitstreams relocation technique (slides: 19, 20) to • speedup the overall system execution • achieve a core preemptive execution • assign at runtime the bitstreams placement • reduce the amount of memory used to store partial bitstreams

  19. Relocation: Virtual homogeneity

  20. Runtime scenario: an example Reconfigurable Functional Unit FPU1: required for 3.65s JPEG: required for 3s FPU2: required for 3.13s 3DES: required for 1s Incoming requests (RFU, request time): (FPU1, 0), (FPU1, 0.1s), (JPEG, 0.1s), (3DES, 0.3s) (a): No relocation (b): Relocation (a) Total Time = R(FPU1) + R(JPEG) + E(JPEG) + R(FPU2) + E(FPU2) = 7.53s (b) Total Time = R(FPU1) + R(JPEG) + R2(FPU2) + E(FPU2) = 4.53s Speed-Up=1.66

  21. OS-based management of dynamic reconfiguration • Provide software support for dynamicpartialreconfiguration on Systems-on-Chip running an operatingsystem (i.e., LINUX). • OS customization for specificarchitectures • Partialreconfigurationprocess management from the OS • Addition and removal of reconfigurablecomponents • Automaticloading and unloading of specific drivers for the IP-Coresuponcomponentsconfiguration and/or de-configuration • Hardware-independentinterface for software developersbased on the GNU/Linux • Easierprogramminginterface for specific drivers

  22. Demonstration and Use • Use threecomplexapplications from differentapplicationdomains and on commercial platforms: • Reverse Time Migration (RTM), a computationalseismographyalgorithm (Maxeler, high-performance) • Global Illumination and Image Analysis (ST, desktop) • Network IntrusionDetection System (Synelixis, embedded) • Evaluate the FASTER tool flow on designer productivity in the design and verificationprocess. • Metrics: applicationspeed, cost, and powerconsumption

  23. Expected Results and Conclusions • FASTER is a focusedprojectthatbuilds on combinedpartners expertise aswellas on pastresearch work and projects • We focus on (and hope to demonstrate): • productivityimprovement in implementation and verification of dynamicallychangingsystems • totalownershipcostreduction (NIDS and RTM systems) • performance improvement under powerconstraints for Global Illumination and Image Analysis application

  24. Challenges & Opportunities • Toolsupport for analysis and systemdefinition • Specification of changingsystem(s) • Reconfigurablegranularity: influenced by (influences???) tools and applications • Architecturalsupport for reconfiguration (vendor?) • Metrics: include design effort/time, totalownershipcost

  25. End… http://www.fp7-faster.eu/

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