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Constructing Current-Based Gate Models Based on Existing Timing Library

Constructing Current-Based Gate Models Based on Existing Timing Library. Andrew Kahng, Bao Liu, Xu Xu UC San Diego http://vlsicad.ucsd.edu. Outline. Gate Modeling Background Problem Formulation Approximation and Regression Applications Experiments Conclusion. Gate Models.

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Constructing Current-Based Gate Models Based on Existing Timing Library

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  1. Constructing Current-Based Gate Models Based on Existing Timing Library Andrew Kahng, Bao Liu, Xu Xu UC San Diego http://vlsicad.ucsd.edu

  2. Outline • Gate Modeling Background • Problem Formulation • Approximation and Regression • Applications • Experiments • Conclusion

  3. Gate Models • K-factor lookup tables • Dg = f(Cload, Tr) • Trout = g(Cload, Tr) • EfficientcapacitanceCefffordistributed load capacitance • To achieve identical gate delay (and output signal transition time at the same time!) • E.g., by achieving the same average gate output current

  4. Calculating Effective Capacitance Ceff = Cload • If (Ceff > Cload || Ceff < 0) • Return Cload • Else if(DCeff < e) • Return Ceff • Else • Continue iteration Trout = g(Ceff, Tr) Ceff s.t. Iout(Ceff)=Iout(load) • May not converge • No equivalent gate delay and Trout at the same time • Waveforms are not ramp functions!

  5. MOSFET is a voltage-controlled current source, e.g., as in the alpha-power-law model For a simple inverter, gate output current is given by one of the transistors An equivalent inverter macro-model for an inverting complex gate  current-based gate modeling Current-Based Transistor Model

  6. Consists of a lookup table I(Vi, Vo) and C(Vi, Vo) Transient analysis for output signal waveform Current-Based Gate Modeling Vi Vo R Vi I(Vi, Vo) C Voltage-Based Current-Based

  7. Current-based gate models need additional pre-characterization, e.g., I(Vi, Vo), given by SPICE DC sweep analysis Cadence Effective Current Source Model (ECSM) Synopsys Composite Current Source Model (CCS) Gate Pre-Characterization Rise_transition (template) { index_1: // slew rate index_2: // load cap values: // output Tr ecsm_waveform (name1) { index_3: // output voltage values: // time point } }

  8. Outline • Gate Modeling Background • Problem Formulation • Approximation and Regression • Applications • Experiments • Conclusion

  9. Given gate delays and output slew rates for load caps and input slew rates, find an equivalent current-based gate model, e.g., I(Vi, Vo) and C Constructing Current-Based Gate Model From Existing Timing Libraries Vi I(Vi, Vo) • Dg = f(Cload, Tr) • Trout = g(Cload, Tr) Dg Tr C Cload I Vo Trout Tr C Vi Cload

  10. To find an unknown underlying physical process by a set of measurements Q = C V Inhomogeneous Fredholm integral equations of the first kind Inverse Problem

  11. Integral equations  differential equations Apply interpolation to reduce variables to those in the I(Vi, Vo) lookup table Inverse problem solutions are extremely sensitive to input data perturbations! Inverse problem  Optimization w/ objective A + a S (A: accuracy, S: smoothness, a: weighting factor) Solving an Inverse Problem

  12. Outline • Gate Modeling Background • Problem Formulation • Solution: Approximation and Regression • Applications • Experiments • Conclusion

  13. A priori knowledge: Approximate I(Vi, Vo) by a quadratic polynomial 9+1 coefficients in a limited range Polynomial Regression of I(Vi,Vo)

  14. Polynomial Regression of I(Vi,Vo)

  15. Start with an initial polynomial coefficient For each iteration Perturb a coefficient ai’ = ai + d Compute mean square gate delay mismatch e If e reduces, commit perturbation ai = ai + d Else, go other direction ai = ai – d Stop if no improvement Reduce step d for another iteration Compute I(Vi, Vo) and C Our Constructive Method

  16. Applications • More accuracy, arbitrary waveform • Efficiency advantage over SPICE simulation • Gate delay calculation for • Long interconnects • Cross-coupling interconnects • Supply voltage drop effect • Supply current calculation • Noise calculation

  17. There exists an equivalent inverter macro-model for each input combination for any (inverting) complex gate Adjust input and output voltages for I(Vi, Vo) table lookup for a falling input signal, but not for a rising input signal Supply Voltage Variation Effect on Gate Delay Calculation

  18. Experiments • BPTM 70nm technology cell library • Compare (our) constructed and (SPICE simulation based) pre-characterization models

  19. Experiments • Gate delays by (1) our model and (2) pre-characterized model normalized by SPICE simulation results

  20. Summary • Utilize existing timing libraries for application of novel current-based gate modeling • Wide range of applications: supply current calculation, delay calculation for complex waveforms, e.g., resistive shielding, crosstalk coupling, supply voltage variation, etc. • Slightly less accurate than pre-characterized current-based gate models, e.g., within 8.6% vs. 4.4% for gate delay calculation with varied supply voltage • Reasonable runtime for model construction, 28.3 seconds in average on a 2.8GHz P4 system

  21. Thank you !

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