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ELE 523E COMPUTATIONAL NANOELECTRONICS

Mustafa Altun Electronics & Communication Engineering Istanbul Technical University Web: http://www.ecc.itu.edu.tr/. ELE 523E COMPUTATIONAL NANOELECTRONICS. W7-W8:Defects and Reliability, 11/11/2013-18/11/2013. FALL 2013. Outline. Defects in nanoscale Permanent defects

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ELE 523E COMPUTATIONAL NANOELECTRONICS

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  1. MustafaAltun Electronics & Communication Engineering Istanbul Technical University • Web: http://www.ecc.itu.edu.tr/ ELE 523E COMPUTATIONALNANOELECTRONICS W7-W8:Defects and Reliability, 11/11/2013-18/11/2013 FALL 2013

  2. Outline • Defects in nanoscale • Permanent defects • Transient defects • Defects in logic gates • Bayesian networks for defect modeling • Defects in nano arrays • Defect tolerance in nano arrays

  3. Defects • Defects are the main headache in nanoscale. • Up to 10% defect ratio • Defects are inevitable and must be handled Defects in self-assembled nano arrays

  4. Defects Permanent • Happens before first usage. • Happens mostly in the fabrication and packaging level. • Results in hard error. • Relatively easier to fix • Detecting the defect followed by reconfiguration. • Transient • Happens any time. • Result in hard error. • Result in soft error. • Random defects are harder to fix. • The only way is redundancy. • Dummy devices added. 1 1 0 at any time 1 at t=10s 0 at t=0s 0 at t=2s AND AND 1 1 Hard error Softerror

  5. SoftDefectsin Gates Errorprobabilityϵ: a gateevaluates the incorrect result, the complement of the correct Boolean value, withϵ. Ideally With a defect 0 AND 0 0 0 with a probability of 1-ϵ 1with a probability ofϵ 0 AND 0 1 1 AND 0 0 1 with a probability of 1-ϵ 0with a probability ofϵ 1 AND 1 1

  6. SoftDefectsin Gates Errorprobabilityϵ: eachgateevaluates the incorrect result, the complement of the correct Boolean value, withϵ. Example: What is the probabilityPx that the circuit produces an incorrect result. a OR b x AND c Px = ϵ - (2ϵ2- ϵ)c

  7. SoftDefectsin Gates Errorprobabilityϵ: eachgateevaluates the incorrect result, the complement of the correct Boolean value, withϵ. Example: What is the probability Pythat the circuit produces an incorrect result. a AND c y OR b AND c Py = 3ϵ - 5ϵ2 + 2ϵ3- (ϵ - 2ϵ2)(a+b)c + (2ϵ2 -4ϵ3)abc

  8. SoftDefectsin Gates Both circuits, A and B, implement the same Boolean function (a+b)c. Whichcircuit is better in defecttolerance? A Px = ϵ - (2ϵ2- ϵ)c B Py = 3ϵ - 5ϵ2 + 2ϵ3- (ϵ - 2ϵ2)(a+b)c + (2ϵ2 -4ϵ3)abc

  9. Bayesian Networks for Errors • A, B, C, D, and E can be any circuit part. • Suppose that A, B, C, D, and E are gates. • P(A): Probability that there is an error at the output of A, i.e., the output of A is incorrect. • P(B|A): Probability that theoutput of B is incorrect, given that the output of the gate A is incorrect. • P(E|A,C): Probability that theoutput of E is incorrect, given that the output of the gatesA and C are both incorrect. One-directionalBayesian network to model errors/defects in circuits

  10. Defectsin Nano Arrays Ideally f = A B +CD With a defect f = A B + B CD With a defect f = A +CD Howtotoleratedefects? Each crosspoint is either closed (diode connected) or open. What if a crosspoint is closed when it is supposed to be open? What if a crosspoint is open when it is supposed to be closed?

  11. Defectsin Nano Arrays Ideally f = (A B +CD)ꞌ With a defect f =0 Howtotoleratedefects? Each crosspoint is either closed (MOS orshorted) or open. What if a crosspoint is closed when it is supposed to be open?

  12. Defectsin Nano Arrays Ideally f = x1 x2ꞌx3+ x1 x4ꞌ+ x2 x3 x4ꞌ+ x2 x4 x5 + x3 x5 0 With a defect f = x1 x2ꞌx3+ x1 x4ꞌ+ x2 x3 x4ꞌ+ x2 x4 x5 + x3 x5 1 With a defect f = x1 x2ꞌx3+ x1 x4ꞌ+ x2 x3 x4ꞌ+ x2 x4 x5 + x3 x5 Howtotoleratedefects? Each crosspointis either closed or opendepending on theappliedliteral. What if a crosspoint is alwaysclosed when it is supposed to switch? What if a crosspoint is alwaysopen when it is supposed to switch?

  13. Tolerating Defects in NanoArrays • OFF-to-ON defect: The switch is ON when it is supposed to be OFF; x1=0. • ON-to-OFF defect: The switch is OFF when it is supposed to be ON; x1=1. • Each switch of the lattice has independent defect rates.

  14. Tolerating Defects in NanoArrays • Ideally, ifx1=0then all the switches are OFF. • Ideally, ifx1=1then all the switches are ON. • We use redundancy in tolerating defects powered by percolation.

  15. Percolation Theory Rich mathematical topic that forms the basis of explanations of physical phenomena such as diffusion and phase changes in materials. Broadbent & Hammersley (1957).

  16. Percolation Theory Sharp non-linearity in global connectivity as a function of random local connectivity.

  17. Percolation Theory p2versusp1for1×1, 2×2, 6×6, 24×24, 120×120, and infinite size lattices. • Each square in the lattice is colored black with independent probabilityp1. • p2is the probability that a connected path exists between the top and bottom plates.

  18. Margins • One-margin: Tolerable p1ranges for which we interpret p2as logical one. • Zero-margin: Tolerable p1ranges for which we interpret p2as logical zero. Margins correlate with the degree of defect tolerance.

  19. Implementing Boolean Functions signals in:xi’s signals out: connectivity top-to-bottom / left-to-right.

  20. An Example with 16 Boolean Inputs A path exists between top and bottom, fL= 1

  21. Margin Performance with a 2×2 Lattice fL=x1x3+x2x4 gL=x1x2+x3x4 Different assignments of input variables to the regions of the network affect the margins.

  22. One-margins (always good) ONE-MARGIN fL=0 fL=1 Defect probabilities exceeding the one-margin would likely cause an (1→0) error.

  23. Good Zero-margins ZERO-MARGIN fL=0 fL=1 Defect probabilities exceeding zero-margin would likely cause an (0→1) error.

  24. Poor Zero-margins POOR ZERO-MARGIN fL=1 fL=0 Assignments that evaluate to 0 but have diagonally adjacent assignments of blocks of 1's result in poor zero-margins

  25. Lattice Duality A necessary and sufficient condition for good error margins is that the Boolean functions fLand gLare dual functions.

  26. Lattice Duality fL=x1x3+x2x4 gL=x1x2+x3x4 fL ≠ gLD

  27. Suggested Readings • Moore, E. F., & Shannon, C. E. (1956). Reliable circuits using less reliable relays. Journal of the Franklin Institute, 262(3), 191-208. • Von Neumann, J. (1956). Probabilistic logics and the synthesis of reliable organisms from unreliable components. Automata studies, 34, 43-98. • DeHon, A. (2003). Array-based architecture for FET-based, nanoscale electronics. Nanotechnology, IEEE Transactions on, 2(1), 23-32. • Altun, M., & Riedel, M. D. (2011). Robust Computation through Percolation: Synthesizing Logic with Percolation in Nanoscale Lattices. International Journal of Nanotechnology and Molecular Computation (IJNMC), 3(2), 12-30.

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