Concluding Remarks

1. Concluding Remarks SOAP CSE 141 - Final Remarks

2. Computer Technologies • First Generation: Mid 40’s to late 50’s • Vacuum Tube “switches” • Acoustic or CRT memory (volatile) • Second Generation: Late 50’s to mid 60’s • Individual transistors • Core memory, magnetic disks (non-volatile) • Third Generation: Mid 60’s to mid 70’s • Integrated circuits (up to 1000 transistors/chip) • Complex instructions via microcode • Fourth Generation: Mid 70’s and beyond • single-chip processors; semiconductor memory CSE 141 - Final Remarks

3. Computer Taxonomy • Supercomputer • Parallel or vector machine, fast memory, cost > $1 M • Mainframe, Server • Typically serve 100’s of users; lots of I/O power • Workstation • High performance; less I/O than mainframe • 1-10 users, often UNIX operating system • Personal Computer • Single user, < $3000, often Microsoft or MAC OS. • Embedded computer or controller • Special-purpose interface: gameboys, microwaves, ... The difference between these two is disappearing CSE 141 - Final Remarks

4. The computer pyramid There are far more lower-layer computers than higher, more powerful ones. Innovations move from top to bottom (usually). But supercomputers are being replaced by interconnected workstations & PC’s (and Playstations??). Super – computers Servers Workstations Personal Computers Embedded Controllers CSE 141 - Final Remarks

5. What is all about? this course architecture • Layers of Abstraction • ISA’s, bus standards (e.g. PCI, Ethernet, ...), Virtual Memory • Good (or popular) standards evolve and outlive individual machines • E.g. IBM 360, Intel x86 • Interfacing We’ve had to consider programming languages, compilers, operating systems, networks, ... • Performance ... CSE 141 - Final Remarks

6. Memory Evolution A slide from beginning of course • Transistors get smaller, resulting in ... • DRAM chip capacity doubles every 1.5 years • Transistor count doubles every 2 years • Clock speed doubles every 3 years • Memory speeds increase a tiny bit And then a miracle occurs ... • Performance doubles every 1.5 years Processor Evolution CSE 141 - Final Remarks

7. Processor Architecture Load Store Program Counter Registers Instruction Register Control ALU CSE 141 - Final Remarks

8. pipeline the ALU Load Store Program Counter Registers Instruction Register Pipe- lined ALU Control CSE 141 - Final Remarks

9. separate fixed & float Load Store Program Counter Integer Registers Float Registers Instruction Register Integer pipe Floating Point pipe Control CSE 141 - Final Remarks

10. add branch prediction Load Store Program Counter Integer Registers Float Registers Instruction Register Control + Branch Prediction Integer pipe Floating Point pipe CSE 141 - Final Remarks

11. out-of-order execution Load Store Program Counter Integer Registers + shadow registers Float Registers + shadow registers Instruction Register File Control, Branch Prediction, OutOfOrder Integer pipe Floating Point pipe CSE 141 - Final Remarks

12. Integer pipe Floating Point pipe Floating Point pipe more functional units Load Store Load Store Load Store Program Counter Integer Registers + shadow registers Float Registers + shadow registers Instruction Register File Control, Branch Prediction, OutOfOrder Integer pipe CSE 141 - Final Remarks

13. Integer pipe Floating Point pipe Floating Point pipe on-chip memory caches TLB Load Store Load Store Load Store ProgramCounter Level2 Cache Integer Registers + shadow registers Float Registers + shadow registers Instruction Register File Data Cache Instruction Cache Control, Branch Prediction, OutOfOrder Integer pipe CSE 141 - Final Remarks

14. Speculation What has changed? Amount of on-chip concurrency What hasn’t changed (yet)? The program counter Coming to your computer soon ... Multithreaded ArchitecturesSmall changes to microprocessor: - add 3 - 7 program counters and register sets CSE 141 - Final Remarks

15. The Final • Tuesday, March 19, 11:30 – 2:29 • Last names A – M : Center 113 (classroom) • Last names N – Z : CSB 001 (section room) • You may bring: • 3 pages of handwritten notes • Calculators (though I still don’t understand how they help!) • A little odorless food CSE 141 - Final Remarks

16. What’s on the Final ?? • Entire course • Including things that weren’t on quizzes: • E.g. branch hazards, superscalar scheduling • Similar to quizzes: • Some easier questions, some harder • Vocabulary, details (control lines, cache operation, ...), reasons for various choices, calculations. • Including a BotEE (Back of the Envelope Estimate) Note: For other problems, don’t round off answers CSE 141 - Final Remarks

17. System bus Processor and Caches Memory Ethernet #1 Ethernet #2 Ethernet Controller remote sensors remote sensors Quiz 3, last question • Data moves from Ethernet Controller to Memory on System Bus. • Only one pair of devices can use a bus at a time. • So, processor-memory communication is disrupted. • Total amount of data moved on System Bus per image 1 MByte: Ethernet Controller to Memory 1 MByte: Memory into Cache first time (compulsory misses) 2 MByte: Extra trips of data into cache (it keeps getting kicked out) 4 MByte total Total system speed is limited by: With Fast Ethernet, getting data from cameras to Ethernet Controller With Gigabit Ethernet, the System Bus limits performance CSE 141 - Final Remarks

18. Grading Quiz 1 Hi 27.5 (out of 30) Top quartile: 21.5 Median: 18 Third Quartile: 15 Quiz 2 High 38 (out of 40) Top quartile: 34 Median: 31.5 Third quartile: 27.5 Quiz 3Hi 28 (out of 29) Top quartile: 20 Median: 17.5 Third quartile: 15 Add 10 to Quiz 1 score Add 11 to Quiz 1 score 30 is “B” (and closer to B+ than B-) CSE 141 - Final Remarks