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Static Analysis of HDL Descriptions: Extracting Models for Verification

ISP. RAS. Static Analysis of HDL Descriptions: Extracting Models for Verification. Alexander Kamkin Sergey Smolov Igor Melnichenko. Introduction. Functional verification is a bottleneck of HW design process Different models are used for verification Built from requirements

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Static Analysis of HDL Descriptions: Extracting Models for Verification

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  1. ISP RAS Static Analysis of HDL Descriptions: Extracting Models for Verification Alexander Kamkin Sergey Smolov Igor Melnichenko

  2. Introduction • Functional verification is a bottleneck of HW design process • Different models are used for verification • Built from requirements • Extracted from HDL • EFSM-based models are intensively used in verification East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013

  3. Extended Finite State Machine: FIFO example East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013

  4. Related work • EFSM extraction for synthesis • Dependencies elimination [Giomi, 1995] • EFSM extraction for functional test generation • Backtracking [Guglielmo et al., 2011] • RTL-to-TLM abstraction in mutation testing • FAST framework [Bombieri et al., 2012] East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013

  5. EFSM extraction method • Inner Representation elaboration • IR-to-Guarded Action transformation • Guarded Actions dataflow analysis • EFSM building East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013

  6. Inner Representation-to-Guarded Action transformation • Clock-like inputs analysis • Splitting on “wait” statements • For each process set is generated • Guards – conditions of branches (if no such, ) • Actions – branch statements East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013

  7. IR-to-GA transformation: example East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013

  8. Guarded Actions dataflow analysis • Data Flow Graph – basic structure for state-like registers analysis East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013

  9. EFSM building (1) East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013

  10. EFSM building (2) • Action1: Destination is: • Action3: Guards for transitions: East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013 10/14

  11. Experiments • EFSM extraction tool was implemented • JUNG – data flow graph analysis • ZamiaCAD – IR extraction • 4 open-source VHDL designs were analyzed • 42 modules, 14 KLOC • 25% of modules – adequate EFSMs were extracted East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013

  12. Conclusion • We have suggested the method for extracting EFSMs from HDL • Automated extraction of: • clock inputs • state registers • We have successfully extracted EFSMs from HDL modules East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013

  13. Contacts • Institute for System Programming RAS http://www.ispras.ru • Hardware Verification Group http://hardware.ispras.ru • Sergey Smolov ssedai@ispras.ru East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013

  14. Thank you! Questions? East West Design and Test Symposium, Rostov-on-Don, September 27-30, 2013

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