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Radiation tolerance of commercial 130nm CMOS technologies for High Energy Physics Experiments

Radiation tolerance of commercial 130nm CMOS technologies for High Energy Physics Experiments. Federico Faccio for the CERN(PH/MIC)-DACEL * collaboration. * DACEL is an INFN project involving the INFN sections of Bari, Bergamo, Bologna, Firenze, Padova, Pavia and Torino. Outline.

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Radiation tolerance of commercial 130nm CMOS technologies for High Energy Physics Experiments

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  1. Radiation tolerance of commercial 130nm CMOS technologies for High Energy Physics Experiments Federico Faccio for the CERN(PH/MIC)-DACEL* collaboration * DACEL is an INFN project involving the INFN sections of Bari, Bergamo, Bologna, Firenze, Padova, Pavia and Torino

  2. Outline • Past, present and future: • 250nm CMOS with HBD approach for the LHC experiments • Motivation for moving to 130nm CMOS • Irradiation results (TID) for 3 different manufacturers (Foundries) • SEE results • Conclusion F.Faccio

  3. TID effects in CMOS technologies (1) Parasitic MOS 2. Effects in the thick lateral isolation oxide (STI) between source and drain of a transistor Parasitic channel Field oxide Bird’s beak Source Drain 1. Effects in the thin gate oxide F.Faccio

  4. TID effects in CMOS technologies (2) Metal 1 Metal 1 STI OXIDE STI OXIDE STI OXIDE N+ diffusion N+ diffusion N+ diffusion STI STI N+ diffusion N+ diffusion N+ diffusion + + + + + + + + + + + + + + SUBSTRATE SUBSTRATE 3. Effects in the isolation oxide (STI), in between n-well or diffusions F.Faccio

  5. Past and present: 250nm CMOS G S D Hardness By Design (HBD) approach has been used: ELT transistors F.Faccio

  6. Past and present: 250nm CMOS G V V V SS SS DD OXIDE + + + + + + N+ DRAIN + + P+ GUARD N+ SOURCE + + + + p+ guardring S D SUBSTRATE Hardness By Design (HBD) approach has been used: guardrings F.Faccio

  7. HEP Foundry Service in 250nm CMOS • MPW service organized for more than 100 different ASICs • More than 20 different designs in production (some are multi-ASIC) • More than 2000 wafers (8-inch) produced! F.Faccio

  8. Motivation to move to 130nm • LHC upgrades & SLHC will require higher-performance ICs, tolerant to larger TID levels • 250nm is already an old process and will not stay around much longer • More-modern CMOS processes have the potential of higher TID tolerance and much better performance • What is the radiation tolerance? HBD needed? F.Faccio

  9. Outline • Past, present and future • Irradiation results (TID) for 3 different manufacturers (Foundries) • Experimental details • Core transistors, linear layout • Core transistors, ELT • I/O transistors • Need for guardrings… • SEE results • Conclusion F.Faccio

  10. Test structures and measurement setup • 3 commercial 130nm CMOS processes: foundries A,B and C • Some are PMDs from foundry, some custom-designed test ICs • NMOS and PMOS transistors, core and I/O devices (different oxide thickness), FOXFETs • Testing done at probe station – no bonding required • Irradiation with X-rays at CERN up to 100-200Mrad, under worst case static bias • Further studies (p source, reliability, SEGR, noise, …) are under way F.Faccio

  11. Core NMOS transistors, linear layout (1) • Narrow transistors (W < 0.8mm): • An apparent Vth shift (decrease) for narrow channel transistors • The narrower the transistor, the larger the Vth shift (RINCE) Foundry A, 0.16/0.12 • Wide transistors (W > 1mm): • When the transistor is off or in the weak inversion regime: • Leakage current appears (for all transistor sizes) • Weak inversion curve is distorted Foundry A, 2/0.12 F.Faccio

  12. Core NMOS transistors, linear layout (2) annealing pre-rad pre-rad • Effect on the leakage current • Peak in leakage at a TID of 1-5Mrad • Peaking dependent on dose rate and temperature, difficult to estimate in real environment Foundry A Foundry B Foundry C F.Faccio

  13. Core NMOS transistors, linear layout (3) • Effect on the threshold voltage • Peak in Vth shift at a TID of 1-5Mrad (A and C) • The narrower the transistor, the larger the Vth shift (RINCE) • Peaking dependent on dose rate and temperature, difficult to estimate in real environment Foundry A Foundry B Foundry C F.Faccio

  14. Radiation-induced edge effects - NMOS E field lines E field lines Polysilicon Polysilicon gate gate - - + + + + ID - - + + + + STI STI - + + - + + STI STI Oxide trapped charge Interface states Depletion region Depletion region Main transistor Lateral parasitic transistor 0 VGS F.Faccio

  15. Core PMOS transistors, linear layout (1) Foundry A, 0.16/0.12 • No change in the weak inversion regime, no leakage • An apparent Vth shift (decrease) for narrow channel transistors • The narrower the transistor, the larger the Vth shift Foundry B, 0.14/0.13 Foundry C, 0.28/0.12 F.Faccio

  16. Radiation-induced edge effects - PMOS E field lines E field lines Polysilicon Polysilicon gate gate - + + + + + ID - + + + + + STI STI + + + + + + STI STI Oxide trapped charge Interface states Depletion region Depletion region Main transistor Lateral parasitic transistor 0 VGS F.Faccio

  17. Core NMOS transistors, enclosed layout (ELT) Example: Foundry A • The radiation hardness of the gate oxide is such that practically no effect is observed – verified for 2 foundries (A up to 140Mrad, B up to 30Mrad) F.Faccio

  18. I/O transistors, linear layout Foundry A, NMOS 0.36/0.24 • Large effect for all sizes, but more important for narrow channel transistors • Results different with Foundry, but for all enclosed layout is required already for TID levels of the order of 50-100krad (NMOS) • Effect is not negligible also for ELTs: relevant Vth shift! Foundry A, PMOS 2/0.24 F.Faccio

  19. Are guardrings systematically needed? (1) • FoxFETs are “Field Oxide Transistors” • Good to characterize isolation properties with TID • Structures available in only 1 technology (1 only Foundry) 1. N+diffusion to N+diffusion (source/drain of two neighbor NMOS transistors) F.Faccio

  20. Are guardrings systematically needed? (2) G G D D D S S S Metal 1 Metal 1 STI OXIDE STI OXIDE STI OXIDE N+ WELL CONTACT N+ WELL CONTACT N+ WELL CONTACT N+ diffusion STI oxide STI oxide + + + + + + + + + + N WELL N WELL N WELL SUBSTRATE SUBSTRATE Vg=2.5V Vg=2.5V 2. N+diffusion to Nwell (Nwell with PMOS logic to drain/source of NMOS logic) F.Faccio

  21. Are guardrings systematically needed? (3) Vdd Vdd Vdd N-well N-well N-well Realistic test structure with series of Inverters + DFF along 350um, and with different separation between n-well (PMOS logic) and NMOS: Without guardring Partial guardring Full guardring F.Faccio

  22. Are guardrings systematically needed? (4) F.Faccio

  23. Outline • Past, present and future • Irradiation results (TID) for 3 different manufacturers (Foundries) • SEE results • Conclusion F.Faccio

  24. SEE results: the SRAM circuit • 16kbit SRAM test circuit designed using the SRAM generator from a commercial library provider – not dedicated rad-tolerant design! • Test performed with Heavy Ions at the Legnaro National Laboratories accelerator in June 2005 F.Faccio

  25. Heavy Ion irradiation results • Test at Vdd=1.5 and 1.25 V, results very similar • Sensitivity to very low LET values (threshold below 1.6 MeV/cm2mg) • Comparison with 0.25mm memory (rad-tol design!!): • Cross-section 15-30 times larger in LHC environment F.Faccio

  26. Challenges for 130nm • Technology more expensive than ¼ micron: • Strong push for first working silicon • Strong push for common solutions to similar problems • Technology more complex than ¼ micron: • Reduced Vdd, difficult for analog • Physical effects can not be ignored: proximity effects, filling requirements, “cheesing”, … • As a consequence, design rules are considerably more complex (impressive growth of the design manual) • Larger number of tools is needed • Competence in radiation effects are also required • If non-enclosed transistors are used • To protect circuits from SEEs • All competences in technology, design techniques and tools necessary for a successful project are more difficult to gather in a group of small size F.Faccio

  27. Conclusion • HBD in quarter micron has made LHC electronics possible/affordable: large scale application of HBD is a reality! • Natural radiation tolerance of 130nm better than for the quarter micron technology (not for I/O transistors), but Mrad-level still requires HBD for reliable tolerance • Large effort required to develop library, acquire tools, master the technology: • Working with 130nm is MUCH more complex and expensive; pressure to get quickly to working silicon • CERN is preparing a frame contract with 1 selected Foundry, to develop library/design kit/design flow serving the whole HEP community F.Faccio

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