Part B Presentation Winter 2011 ASIC Tester Performed by : AboRaya Dia Damouny Samer

1. High Speed Digital Systems Lab in collaboration with VLSI Lab Electrical Engineering Department, Technion Part B Presentation Winter 2011 ASIC Tester Performed by : AboRayaDia DamounySamer Supervised by: Ina Rivkin

2. Overview : • Objective: testing the ASIC’s functional correctness • Comparing the provider’s input with the expected outputs • Providing options for viewing and analyzing the results

3. Technical specifications : • The tester supports up to 96 inputs/outputs and up to • 48 bi-directional pins. • Samples I/O signals up to 50 MHz rate. • 1G memory for inputs. • 1G memory for outputs.

4. Project goals : 0. Designing a basic design for sending/receiving data to/from the DUT . 1. Adding the loop mode to the basic design. 2. Adding Embedded Logic Analyzer . 3 . Defining a new GUI . 4. Writing the new GUI .

5. Block Diagram : Host application PCI BUS PCI BUS FPGA PSDB DUT

6. The loop command • Main components of the design : • Register File for saving the loop commands ( size = 64 * 97 bit ) . • Internal RAM ( cache ) for part of the data that will be sent to the DUT ( 8192 * 96 bit = 0.75 mega bit ) . • A FIFO to save the outcome of the DUT and before sending them to the DDR . • 4. In addition , we have 3 controllers : • Read from DDR : Reading data from DDR and writing it to the RAM. • Read from RAM : Reading the data from the RAM , sending it to the DUT (according to the loop commands) , and writing the results to the FIFO. • Read from FIFO : Reading the results from the FIFO and sending them to the DDR.

7. FPGA Block Diagram – Including Loop Command 50 MHz DDR A FPGA PSDB 96 bit Internal RAM (cache) 96 bit Read from DDR Controller DUT Read from RAM Controller 97 bit Register File Write to FIFO out Controller DDR B FIFO 96 bit 7

8. FPGA Block Diagram – Including Loop Command 50 MHz DDR A FPGA PSDB 96 bit Internal RAM (cache) 96 bit Read from DDR Controller DUT Read from RAM Controller 97 bit Register File Write to FIFO out Controller DDR B FIFO 96 bit 8

9. FPGA Block Diagram – Including SignalTap And Configuration unit 50 MHz Config unit FPGA DDR A 96 bit Internal RAM (cache) Read from DDR Controller Clk0=200MHz DUT SignalTap Clk2=50MHz Read from RAM Controller Register File Counter Write to FIFO out Controller DDR B FIFO Config registers 9

10. Configuration unit-in/out Data_in(i) Config unit Data_out(i) Data to pin out 96 bit Configuration • When configuration = ‘1’ then • Data_to_pin_out = data_out • When configuration = ‘0’ then • Data_in = data_to_out_pin

11. Configuration unit-InOut Data_in(i) Config unit Data_out(i) Data to pin out 96 bit In 1 Config[0] Config(2 bit) In 0 • The same as before, but now with mux that will choose the in/out or real-time configuration. • The real-time configuration will be given in the data vector. Config[1]

12. Configuration unit-the whole Unit • The Config unit is duplicated 96 times. Config unit Config unit Tester moudle Config unit Config_reg_en Config unit

13. Configuration unit-internal connectivity Tester moudle Data_in 96 bit Config unit Data_in(i) Data_out 96 bit Data_out(i) Data to pin out 96 bit Data_out(i+48) In 1 Config(i) (2 bit) Config(i) (LSB bit) In 0 Config_reg_en Config(i) (MSB bit) Config 96*2 bit 13

14. Short-circuit on PSDB • Short circuit connects 24 pins with each others (12 pins to 12 pins). • This is the basic test of the Tester. Connectors Short circuit PSDB

15. Connecting DUT to 96 pins • Connecting the DUT should be according to the table. • For example: • pin ‘a’ of the DUT connected to pin number ‘1’ in the data_out vector recalls that the PSDB pin is l1(46) and the pin number on the connector is 81 • Should look at the table in the final report to see this mapping and Proce data book page 27

16. Connecting the DUT to the clock Clk2 which is the design clock is connected to the psdb via 2 pins. Pin number 2 and 120 in j5/j6 connectors . User can connect DUT clock to these pins and this DUT will be derived by the same clock as the design.

17. Data creating Datain Data out • Every vector is 96 bit. • Data out vector is the data that will be injected to the DUT. • Data in vector is the DUT output. • When pin with index i is an output then Data_out[i] = value and Data_in[i] should be ignored. • When pin with index i is an input then Data_out[i] should be ignored and Data_in[i]=result. • When pin with index i is inout then Data_out[i+48] must contain the polarity of this pin in every cycle. Don’t care 1 1 Don’t care

18. Configuration Configurationregisters • When port “i” is out, the register i should contain the value 00. • When port “i” is in, the register i should contain the value 01. • When port “i’ is inout, the register i should contain the value 10 . 0 1 00 -> out 01 -> in 10 -> inout 11 -> not in use

19. Starting: Signal tap When “ready to acquire” is shown , the signal tap is ready to use, to be ready, user should load the design into the PROCe FPGA. To start using signal tap, user should choose this instance (left click) .

20. Setup tabPhysical pins and trigger counter • In this tab, user can see the signals that will be sampled, and choose the trigger condition. • 96 pins which are connected to the DUT and trigger counter can be used to enable trigger sampling. 2 options : • counter: assign value(n) to the output count, when the n’th output is being injected, the trigger will be enabled. • pin value/transition : choose a value/transition of one or more pin. • Transition means signal changed from ‘1’ to ‘0’ or from ‘0’ to ‘1’

21. Signal configuration User should choose hardware for the trigger: Always choose USB-Blaster. • Sampling clock : don’t change it. • Sampling depth . • Storage qualifier . • (changing sampling clock or sampling depth requires design compelation ) • Trigger position : • Define percentage of the data storage before • And after the trigger, 3 options: • Pre : 20% of the data is before the trigger • post : 80% of the data is before the trigger • center : 50% of the data is before the trigger

22. Example Go to the data tab to see signals values when trigger happen

23. The Tester application • Allow the user to: • Determine the test vectors • Configure the application for the DUT and save the configuration for reuse • View results and compare with wanted outputs (list of all the features can be found in the report) • Application User Interface: • Our application will have two main screens: • Configuration • Debug • Our application will interact with the user through these screens

24. Main Screen

25. Configuration mode screen

26. Configuration mode screen • The main part of the application. • Allows the user to configure the system parameters to the PSDB and DUT, and to save them in a configuration file (for further use) • For each DUT that has a saved configuration file , the user will not need to reconfigure it, only to load the file. • Creates the “Database” for results analysis. • The application fills the relevant registers with the configuration information for the HW (according to protocol).

27. Configuration mode – Loading configuration file

28. Configuration mode – Pins table • The user will add inputs and outputs to the pins table • The pins (or buses) will be added with a name (decided by the user) • The user will fill the test values (in the .csv file) according to the names given in this pins table

29. Configuration mode – Pins table Type of Vector – IN/OUT/INOUT Header – Vector Name PSDB Mapping DUT Mapping Length of Vector

30. Debug mode Screen • The I/O part of our application. • This mode allows the user to: • Load inputs file • Load Loop command . • Generate Wave (Generate new input file based on wave ). • Run the tester and save the outputs • Generate expected outputs based on loop . • Load wanted outputs (golden model) • Load logic analyzer . • Compare outputs (in cycles) • Single Step Mode • All files created are of .csv (comma-separated values) type.

31. Debug mode

32. Debug Mode – Load inputs file

33. Debug Mode – Load inputs file • The user will load the inputs (test vectors) through a .csv file • .csv is can be created through Microsoft Office Excel (instead of .xslx file) • Example: • A is an 4 bit input bus • B is a one bit input pin • C is a 3 bit input bus • Each line represents aninput cycle and producesan output value

34. Debug Mode – Load Loop commands

35. Debug Mode – Load Loop commands • The user will load the loop commands through a .csv file Start line repeat End line

36. Debug Mode – Generate Waves

37. Debug Mode – Generate Waves • Generate new inputs file based on the selected wave and values . • Example : const random clk counter

38. Debug mode – Run and Save Outputs

39. Debug mode – Run and Save Outputs • The application will activate the HW, read the outputs from Bank B and create a .csv file with the outputs. Pin 95 in PSDB Pin 46 in PSDB

40. Debug Mode – Functionality test 1 2

41. Debug Mode – Functionality test • Load Wanted Outputs & Compare : After running the tester and saving the outputs to .csv file , the user can load wanted outputs file (“ Golden reference”) in order to compare between the two files and produce a comparison report .

42. Debug Mode – Functionality test • Load Logic Analyzer : The signalTap LA will be loaded :

43. Debug Mode – Functionality test • Load Logic Analyzer : When running the tester , the user will be asked to click on the Run Analysis button :

44. Debug Mode - Single Step mode Number of Cycles to run Max Cycles to run Cycles counter Inputs according to input file