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Unit 3 Finite State Machine

Unit 3 Finite State Machine. If we hear, we forget; if we see, we remember; if we do, we understand. -- Proverb. 3.1 Derivation of State Graphs and Tables.

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Unit 3 Finite State Machine

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  1. Unit 3 Finite State Machine If we hear, we forget; if we see, we remember; if we do, we understand. -- Proverb Department of Communication Engineering, NCTU

  2. 3.1 Derivation of State Graphs and Tables Department of Communication Engineering, NCTU

  3. A Finite State Machine (FSM) is simply a state register that holds the current state and some combinational logic which calculates the next state and outputs based on the current state and the inputs • FSM types • Moore machine : the outputs are functions of the present state only • Mealy machine : the outputs are functions of both the present state and the inputs Department of Communication Engineering, NCTU

  4. Initialization Easy Cards Passing Locked Unlocked Passing Violation (Unlocked) Alarm Reset • A Moore FSM • MTS turnstile Department of Communication Engineering, NCTU

  5. State diagram representation • Locked ST: S0,Unlocked ST : S1and Violation ST: S2 • Inputs • Presence of Easy Card  u0 =1, otherwise u0 =0 • Passenger passing  u1 =1, otherwise u1 =0 • Alarm reset  u2 =1, otherwise u2 =0 • Outputs (Z) • S0 Locked • S1 Unlocked • S2 Unlocked u0=0 XNOR u1=0 S0 u0=1 u1=1 u2=1 u1=1 S2 S1 u1=0 u2=0 Department of Communication Engineering, NCTU

  6. u0=0 XNOR u1=0 S0 u0=1 u1=1 u2=1 u1=1 S2 S1 u1=0 u2=0 • State transition table Department of Communication Engineering, NCTU

  7. Binary state assignment Department of Communication Engineering, NCTU

  8. Next-State maps u1u0 u1u0 01 11 10 01 11 10 Q1Q0 Q1Q0 00 00 01 01 u2 1/0 u2 1/0 11 11 10 10 Q1+ Q0+ Department of Communication Engineering, NCTU

  9. Characteristic equations • Q1+= Q1u2’ + Q0’u2’u1u0’ Q0+= Q0u1’ + Q0u0 + u2’u1’u0 u1u0 u1u0 00 00 01 11 10 01 11 10 Q1Q0 Q1Q0 00 00 01 01 u2 1/0 u2 1/0 11 11 10 10 Q1+ Q0+ Department of Communication Engineering, NCTU

  10. Output equations • Characteristic equations:Q1+= Q1u2’ + Q0’u2’u1u0’ Q0+= Q0u1’ + Q0u0 + u2’u1’u0 • Output equation :Z = Q1 Q0 (or = (Q1|| Q0)’ Department of Communication Engineering, NCTU

  11. D D Q Q CK CK CLR CLR • Circuit realization with D-FFs • Characteristic equations:Q1+= Q1u2’ + Q0’u2’u1u0’ Q0+= Q0u1’ + Q0u0 + u2’u1’u0 • Output equation :Z = Q1 Q0 Q1+ u2 Q1 u1 Z u0 Q0+ u1 u0 Q0 u2 CLK Department of Communication Engineering, NCTU

  12. req > floor u,d,o, t = 1,0,0,0 GoingUp !(req > floor) timer < 10 req > floor !(timer < 10) u,d,o,t = 0,0,1,0 Idle DoorOpen u,d,o,t = 0,0,1,1 req == floor req < floor !(req<floor) u,d,o,t = 0,1,0,0 GoingDn u is up, d is down, o is open req < floor t is timer_start • Another Moore FSM • An elevator controller (Up, Down, Open and Timer start) Department of Communication Engineering, NCTU

  13. D D D Q Q Q CK CK CK CLR CLR CLR • The general model of a Moore machine X1 Q1+ Q1 Com. Logic Com. Logic X2 Z1 Xm Q2+ Q2 Z2 Zm Qm+ Qm Department of Communication Engineering, NCTU

  14. A Mealy FSM • A traffic light controller Department of Communication Engineering, NCTU

  15. Tabulation of inputs and outputs • Tabulation of unique states Input Signal Reset C TS TL Output Signal HG, HY, HR FG, FY, FR ST Description place FSM in initial state detect vehicle on farmroad short time interval expired long time interval expired Description assert green/yellow/red highway lights assert green/yellow/red farmroad lights start timing a short or long interval Description Highway green (farmroad red) Highway yellow (farmroad red) Farmroad green (highway red) Farmroad yellow (highway red) State S0 S1 S2 S3 Department of Communication Engineering, NCTU

  16. Reset TL’ + C’ S0 TL & C /ST TS/ST S1 S3 TS’ TS’ TS/ST TL & C’/ST S2 TL’ + C • The state diagram S0: HG (FR) S1: HY (FR) S2: FG (HR) S3: FY (HR) Department of Communication Engineering, NCTU

  17. Reset TL’ + C’ S0 TL& C /ST TS/ST S3 TS’ S1 TS’ TS/ST S2 TL& C’/ST TL’ + C • State transition table HG = S0 FR = S0+ S1 HY = S1 FG = S2 HR = S2+ S3 FY = S3 ST = ? Department of Communication Engineering, NCTU

  18. Department of Communication Engineering, NCTU

  19. TLTS TLTS 01 11 10 01 11 10 Q1Q0 Q1Q0 00 00 01 01 C 1/0 C 1/0 11 11 10 10 Q1+ Q0+ Department of Communication Engineering, NCTU

  20. TLTS 01 11 10 Q1Q0 HG = S0 FR = S0+ S1 HY = S1 FG = S2 HR = S2+ S3 FY = S3 ST = Q1Q0’TS + Q1’Q0 TS + Q1’Q0’CTL+ Q1Q0C’TL 00 01 C 1/0 11 10 ST Department of Communication Engineering, NCTU

  21. X1 Com. Logic Z1 X2 Z2 Xm Zm Q1+ Q1 D D D Q Q Q Q2+ Q2 CK CK CK CLR CLR CLR Qm+ Qm • The general model of a Mealy machine Department of Communication Engineering, NCTU

  22. Reset TL’ + C’ S0 Plant TL& C /ST TS/ST S3 ST S1 TS’ TS/ST S2 TL& C’/ST CntPre TL’ + C VDD DN D DN D D Q Q D Counter for TS CK CK CK CK Pre CLR Pre CLR TS Counter for TL TL • Circuit realization using a Mealy machine TS’ CLK FSM Department of Communication Engineering, NCTU

  23. CLK Q1Q0 S0 S1 S2 S3 TL TS C TL’ + C’ Reset HG = S0 S0 TL& C /ST TS/ST ST S3 S1 CntPre TS’ TL& C’/ST TS/ST S2 TL’ + C • Timing diagram using a Mealy machine ST = Q1Q0’TS + Q1’Q0 TS + Q1’Q0’CTL+ Q1Q0C’TL Department of Communication Engineering, NCTU

  24. Plant VDD TL’ + C’ Reset Counter for TS S0 ST TL& C TS ST’ TS TS’ S3 S1 TS’ CLK ST ST ST DN DN Counter for TL ENA ENA D D TS S2 TL& C’ ST’ CK CK Pre Pre TL TL’ + C FSM • An alternative realization with a Moore machine ST = Q1Q0’+ Q1’Q0 Notice: need more states to generate the Pre signal if needed!! Department of Communication Engineering, NCTU

  25. CLK Q1Q0 S0 S1 S2 S3 TL TS C TL’ + C’ Reset HG = S0 S0 TL& C TS ST’ ST S3 S1 TS’ ST ST ST TS S2 TL& C’ ST’ TL’ + C • Timing diagram using a Moore machine TS’ ST = Q1Q0’+ Q1’Q0 Department of Communication Engineering, NCTU

  26. X1 Plant Z1 X2 Z2 XP ZQ IN1 FSM CS1 IN2 CS2 INR CSM • The general model of a digital circuit Department of Communication Engineering, NCTU

  27. D D Q Q CK CK CLR CLR ST • Difference between a Moore machine and a Mealy machine • The outputs of a Moore FSM are synchronized with the CLK, however the outputs of a Mealy machine are not • The disadvantages of Moore FSMs • In general, more states are required to generate outputs • The action of the plant that the FSM controls is always one CLK period lagging behind the control signals • The above two points are right the advantages of Mealy FSMs • The disadvantages of Mealy FSMs • Outputs of FSMs must be sampled with FFs if synchronization is required • Glitches and spikes CntPre Department of Communication Engineering, NCTU

  28. Serial data code converter • Design a code converter that convert an NRZ-coded bit stream to a Manchester-coded bit stream Department of Communication Engineering, NCTU

  29. Reset S0 0 /0 1/1 0/1 1/0 S1 S2 • Realize the code converter with a Mealy machine • Use a clock Clock2 which is twice the data rate • The only two possible input sequences are 00 and 11 Department of Communication Engineering, NCTU

  30. 0 1 1 1 0 0 1 1 0 1 0 1 0 0 1 S0 S1 S0 S2 S0 S2 S0 S2 S0 S1 0 1 1 0 1 0 1 0 0 1 S0 0 /0 1/1 S1 S2 0/1 1/0 • The timing diagram using the Mealy machine CLK2 NRZ Manchester (ideal) Z (actual) Department of Communication Engineering, NCTU

  31. Redesign the data converter with a Moore machine Department of Communication Engineering, NCTU

  32. The timing diagram using the Moore machine Output is one-clock lagging behind the input sequence Department of Communication Engineering, NCTU

  33. 3.2 Data Path and FSM Department of Communication Engineering, NCTU

  34. The general model of a digital circuit X1 Plant Z1 X2 Z2 XP ZQ IN1 FSM CS1 IN2 CS2 INR CSM Department of Communication Engineering, NCTU

  35. A plant usually includes • A data path over which data are processed • A data path may include • An arithmetic and logic unit (ALU) • Registers • Counters • Decoders • Peripherals which may include • Input devices like key boards and mice • Storages devices like memories and disks • Output devices • Communications interface like USB, RS232, and Eithernet • Speaker • Printer • Displays like LCD and 7-segment displays Department of Communication Engineering, NCTU

  36. Data path and FSM go hand in hand in digital design • A signal processing scheme is usually partitioned into a sequence of processing stages • Data path decides the number of stages the data is processed and the paths of data flow in between the stages • Data at the outputs of each stage are stores in registers • The complexity or in other words the levels of logics in each stage decides the processing speed • On the other hand the number of stages decides the processing delay • FSM controls data’s movement in data path Department of Communication Engineering, NCTU

  37. Reg 0 DIP SW CS0 Reg 1 A A > B A MUX CS1 CS4 COMP MUX B Reg 2 B A = B CS2 CS5 Reg 3 S0 S1 S2 S3 • Data path for bubble sorting of 4 words CS3 Department of Communication Engineering, NCTU

  38. Draw a flow chart Idle Load B N St Load A Cnt1=0 Load Data Counter -- Cnt 0 -- B>A Y Load N Cnt3=0 Load LW Cnt0=0 Cnt 0 = 2 N Load HW Cnt1=Cnt0 Cnt 1 -- Department of Communication Engineering, NCTU

  39. CLK Idle St Load Cnt 3 XX 11 10 01 00 Cnt 0 XX 10 Cnt 1 XX 10 • Checking the Timing diagram Department of Communication Engineering, NCTU

  40. Sequential machines are commonly partitioned into data path units and control units • The synthesis of a sequential machine usually includes: • Constructing the datapath units • Designing FSMs to control the data flow • Realizing the control signals • Checking the timing of signals Datapath Unit Datapath Logic Control inputs FSM Control signals Clock DatapathRegisters Department of Communication Engineering, NCTU

  41. 3.3 Algorithm State Machine Department of Communication Engineering, NCTU

  42. Datapath units consist of: • Arithmetic units : • Arithmetic and logic units (ALU) • Storage registers • Logic for moving data : • through the system • between the computation units and internal registers • to and from the external environments • Control units are commonly modeled by • State transition graphs (STGs) • Algorithm state machine (ASM) charts for FSM • A combined control-dataflow sequential machine is modeled by ASM and datapath (ASMD) charts Department of Communication Engineering, NCTU

  43. Algorithm State Machine (ASM) Charts • State transition graphs only indicate the transitions that result from inputs • Not only does ASM display the state transitions, it also models the evolution of states under the application of input datas • An ASM chart is formed with three fundamental elements Department of Communication Engineering, NCTU

  44. Start En C <= C+1 • Both Mealy and Moore machines can be represented by ASM • The outputs of a Moore machine are listed inside a state box • Conditional outputs (Mealy outputs) are placed in conditional output boxes Department of Communication Engineering, NCTU

  45. A sequential machine is partitioned into a controller and a datapath, and the controller is described by an ASM • The ASM chart can be modified to link to the datapath that is under control of the ASM • The modified ASM is referred to as the algorithm state machine and datapath (ASMD) chart • ASMD is different from ASM in that :each of the transition path of an ASM is annotated with the associated concurrent register operations of datapath Department of Communication Engineering, NCTU

  46. An ASMD chart for a up-down counter Up-down counter with asynchronous reset Up-down counter with synchronous reset Count <= 0 Count <= 0 Reset Count <= Count - 1 Count <= Count + 1 Start Start Clr Count <= Count - 1 Up Up Count <= Count + 1 Department of Communication Engineering, NCTU

  47. Start En C <= C+1 • ASM v.s. ASMD charts for a counter with enable ASM chart representation ASMD chart representation Start Count <= Count + 1 En Enable DP Department of Communication Engineering, NCTU

  48. A electronic dice game Department of Communication Engineering, NCTU

  49. Flowchart for dice game Department of Communication Engineering, NCTU

  50. Convert flowchart to state machine chart Department of Communication Engineering, NCTU

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