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Delivering Leading Edge Solutions

Delivering Leading Edge Solutions

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Delivering Leading Edge Solutions

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  1. Delivering Leading Edge Solutions Defining Signoff amidst the EDA-Foundry-Design Vortex Richard Trihy Director Design Methodology

  2. Leading Edge Technology SolutionsComprehensive at 28nm, leadership at 20nm and beyond Available 2013 2014 2015 High Performance Computing 28HPP High Perf Plus 10XM eXtreme Mobility Wired Applications, Networking 14XM eXtreme Mobility 20LPM Low Power Mobile 28SLP Super Low Power Consumer, Wireless, Mobile Computing 28LPS Low Power PolySi

  3. 28SLP Libraries and IPs - Available Today * Similar IP enablement available for 28HPP

  4. 14/20/28nm Digital and Analog/Mixed Signal Design Flows GLOBALFOUNDRIES Downloadable Reference Flows AMS Design Methodology Overview Synthesis Functional Design LDE Aware Flow Double Pattern-Aware Place & Route DPT aware Custom Layout Double Pattern-Aware Extraction & Timing Post Layout Design Validation Mask Decomposition & Physical Verification Physical Verification and Decomposition Libraries, Tool Scripts, Techfiles, Designs methodology proven on multiple tapeouts

  5. Collaboration: ARM Cadence GLOBALFOUNDRIES28SLP Implementation of A12 Core • Implement Cortex-A12 in SoCchip • AMBA bridge • Interrupt controller • System memory • High-speed PLL • Standard Cell Libraries • ARM SC12MC Base • SLVT C30, LVT C30, LVT C38 (RVT C30) • ARM SC12MC High Performance Kit (HPK) • SLVT C30, LVT C30, LVT C34 (RVT C30) • Fast Cache Instances • 11 FCI memorymacrosfor CPU andnonCPU • 1 compiledmemorymacrofor on-chip systemmemory • PLL • Low jitter GLOBALFOUNDRIES PLL • Extensive testand analog monitorinterface

  6. RTL SDC FP Netlist SDC PLACEMENT Netlist SDC Parasitics Layout Donar Quad-core Cortex-A12 Cadence Flow Synthesis & Physical Synthesis RTL Compiler® Physical Logic Equivalence Check Conformal® LEC P&R (GigaOpt, CCOpt, Nanoroute) Encounter® Digital Implementation Parasitics Extraction QRC® signoff signoff signoff Physical Verification PVS® Static Timing Analysis Tempus® Power Analysis EPS®

  7. 28HPP Delivers 3GHz on Dual Core Cortex-A9 Data as measured in lab Actual measured values Lab test setup

  8. 20LPM: Leading Edge Planar Platform for Mobile & Consumer PPA Relative to 28SLP Total Power vs. Frequency POWER 1.5 1.0 0.5 61% Lower 42% Higher speed at same power PERFORMANCE 28SLP 20LPM Relative Total Power 42% Faster 61% PVT Conditions Process = TT VDD = sweep Temp. = 85C Lower power at same speed AREA 2x Higher gate density Frequency (AU)

  9. 14XM FinFET for Power-sensitive Applications Mobile and WirelessMarketApplications Compute, Connect, Storage MarketApplications Multicore GPU Solutions Power/perfOptimized CPU Solutions • 40% less power than 20nm • 60% less power than 28nm • At comparable performance • 20% higher performance than 20nm • 60% higher performance than 28nm • At comparable power

  10. Leading Edge Technology SolutionsAddressing Design Challenges Layout Dependent Effects Available 2013 2014 2015 Finfets High Performance Computing 28HPP High Perf Plus 10XM eXtreme Mobility Wired Applications, Networking 14XM eXtreme Mobility 20LPM Low Power Mobile Double Patterning New MEOL 28SLP Super Low Power Consumer, Wireless, Mobile Computing 28LPS Low Power PolySi

  11. Collaborative Development Relative Performance ARM IP + GF Design Expertise + EDA Vendor = Performance/Power Breakthrough 2.0 1.3 • Design/Technology co-optimization • Rapid iteration based on close collaboration 14XM CortexTMA9 Dual-Core 14XM-9T 28SLP-12T 62% Power Reduction 0.6 0.2 0.4 0.6 0.8 1.0 Relative Total Power 61% Performance improvement

  12. Double Patterning Impact on Extractionand Timing SignoffMust account for modeling of mask overlap Decomposition One Drawn Level Two Masks Mask Shift Methodology Double Pattern Corner Methodology

  13. P&R Implementation FlowsIn Design fixing of DPT odd cycles is a key productivity feature • Odd-cycle violation is a scenario where decomposition cannot resolve colors without color conflict Pull down Menu from Encounter In Design Odd-Cycle Fixing with PVS Violation due to odd-cycle

  14. Advanced Node Variability and Margining ConsiderationsTraditional De-rating Inadequate at Advanced nodes • Modeling and Margining for Random Device Variability • Design and technology trends • Variability increasing as gate area scales down • Fmax increasing with technology scaling • Much more accurate variability modeling and margining methodology required • Industry has progressively moved to more accurate modeling of variability optimistic here Single derate of 10% pessimistic here • Traditional On-Chip Variation (OCV) derates breaks down below 65nm • Optimistic on short paths and pessimistic on long paths • Derate depends on path depth, location, PVT, cell type • AOCV provides more accurate margining methodology for 65nm and below, but …

  15. AOCV does not model variation on Slew/load, nor Hold Variation • SOCV addresses AOCV shortcomings in graph-based STA • Liberty Variation Format to address shortcomings in modeling the impact of input slew and output load on cell delay variation: • LVF models variation as a first order effect: variation is dependent upon same factors as baseline cell delays (arc/slew/load/cell/PVT) • Statistical Hold method under standardization on Liberty TAB • Variation dependence on input slew/output load can be significant and must be modeled

  16. EDA Foundry Collaboration essential for Advanced Nodes • Open Collaboration part of GLOBALFOUNDRIES DNA • Technology Design-Flow Co-development • New Challenges to tackle • FINFETs : Will Miller Effect swamp our .Lib models? • FINFETs: Will EM/IR solutions hold up? • SADP Decomposition: New sources of variation • Margins: LVF rollout

  17. Thank you Email : richard.trihy@globalfoundries.com