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Snooping Protocols: Mechanisms for Cache Coherence in Multi-Core Systems

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18 diapositives · 385 Views · Nov 18, 2012

An in-depth review of snooping protocols, which are critical for maintaining cache coherence in multiprocessor and multicore systems. It covers various types of snooping protocols, including write-invalidate, write-back, and write-update mechanisms. Visuals such as screenshots of the application illustrate these protocols in action. The discussion includes coherence commands based on bus activity, different states like valid and dirty, and an overview of future work focused on improving cache consistency.

#snooping protocols #cache coherence #multiprocessor systems #writeinvalidate #multiprocessor architecture #main memory #cache states #memory consistency
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Snooping Protocols: Mechanisms for Cache Coherence in Multi-Core Systems
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  1. Snooping Protocols Jason Moore

  2. Agenda • Review of Snooping Protocols • Type of system considered • Screen shots of the application

  3. What are snooping protocols? • The idea of issuing coherency commands based on bus activity • Types of snooping protocols • Write-invalidate and write-back • Write-invalidate and write-through • write-update and write-back • write-update and partial write-through • Write-once

  4. Write-Invalidate and Write-Back • 3 states • Read Only • Main Memory is the primary owner but cache has a copy to read • Read-Write • Cache is the only owner. Must invalidate main memory and all other caches that have a copy • Invalid

  5. Write-invalidate and Write-Through • Main Memory is always consistent with most recent value • 2 states • Valid • Invalid

  6. Write-Update and Write-Back • 4 states • Valid-Exclusive • Main Memory has the only copy • Shared Clean • Shared Dirty • Multiple-copies but only one valid block • Dirty • Has been changed and is not shared

  7. Write-Update and Partial Write-Through • Written to memory at the same time it is broadcast to other caches • 3 states • Valid-Exclusive • Shared • Dirty

  8. Write-Once (Goodman 1983) • Write Invalidate and Write-Back except the first time a block is written to main memory is updated to remain consistent • 3 states • Valid • Invalid • Reserved • Dirty

  9. Write-Invalidate and Write-Back: State Diagram Read by other write RO RW read write Write by other Write by other INV

  10. Example

  11. 2 x 5 Commands 7 1 reads x 2 reads x 2 updates x 5 2 reads x 2 updates x 5 1 updates x 5 2 reads x Input File

  12. Screenshots

  13. Screenshots (cont.)

  14. Screenshots(cont.)

  15. Why no demo? • Silly Java mistake • Keeps values from being displayed correctly in the table • Found the problem this morning • Could not fix it in time for class

  16. Future Work • Before Thursday • Fix bug • Add the remaining protocols • After Thursday (?) • Add cache replacement policies • Add experimental protocols

  17. References • Hesham El-Rewini and Mostafa Abd-El-Barr, Advanced Computer Architecture and Parallel Processing,A John Wiley & Sons, Inc, 2005

  18. Thank You