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14:332:331 Computer Architecture and Assembly Language Spring 2005 Week 7

14:332:331 Computer Architecture and Assembly Language Spring 2005 Week 7. [Adapted from Dave Patterson’s UCB CS152 slides and Mary Jane Irwin’s PSU CSE331 slides]. MIPS arithmetic instructions. Instruction Example Meaning Comments add add $1,$2,$3 $1 = $2 + $3 3 operands; exception possible

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14:332:331 Computer Architecture and Assembly Language Spring 2005 Week 7

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  1. 14:332:331Computer Architecture and Assembly LanguageSpring 2005Week 7 [Adapted from Dave Patterson’s UCB CS152 slides and Mary Jane Irwin’s PSU CSE331 slides]

  2. MIPS arithmetic instructions Instruction Example Meaning Comments add add $1,$2,$3 $1 = $2 + $3 3 operands; exception possible subtract sub $1,$2,$3 $1 = $2 – $3 3 operands; exception possible add immediate addi $1,$2,100 $1 = $2 + 100 + constant; exception possible add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; no exceptions subtract unsigned subu $1,$2,$3 $1 = $2 – $3 3 operands; no exceptions add imm. unsign. addiu $1,$2,100 $1 = $2 + 100 + constant; no exceptions multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product divide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = remainder Hi = $2 mod $3 divide unsigned divu $2,$3 Lo = $2 ÷ $3, Unsigned quotient & remainder Hi = $2 mod $3 Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi Move from Lo mflo $1 $1 = Lo Used to get copy of Lo

  3. ALU VHDL Representation entity ALU is port(A, B: in std_logic_vector (31 downto 0); m: in std_logic_vector (3 downto 0); result: out std_logic_vector (31 downto 0); zero: out std_logic; ovf: out std_logic) end ALU; architecture process_behavior of ALU is . . . begin ALU: process begin . . . result := A + B; . . . end process ALU; end process_behavior;

  4. Number Representation • Bits are just bits (have no inherent meaning) • conventions define the relationships between bits and numbers • Binary numbers (base 2) - integers 0000  0001  0010  0011  0100  0101  0110  0111  1000  1001  . . . • in decimal from 0 to 2n-1 for n bits • Of course, it gets more complicated • storage locations (e.g., register file words) are finite, so have to worry about overflow (i.e., when the number is too big to fit into 32 bits) • have to be able to represent negative numbers, e.g., how do we specify -8 in addi $sp, $sp, -8 #$sp = $sp - 8 • in real systems have to provide for more that just integers, e.g., fractions and real numbers (and floating point)

  5. MIPS Representations • 32-bit signed numbers (2’s complement):0000 0000 0000 0000 0000 0000 0000 0000two = 0ten0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten... 0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten... 1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten • What if the bit string represented addresses? • need operations that also deal with only positive (unsigned) integers maxint minint

  6. Review: Signed Binary Representation -23 = -(23 - 1) = 1011 then add a 1 1010 complement all the bits 23 - 1 =

  7. Two's Complement Operations • Negating a two's complement number: complement all the bits and add a 1 • remember: “negate” and “invert” are quite different! • Converting n-bit numbers into numbers with more than n bits: • MIPS 16-bit immediate gets converted to 32 bits for arithmetic • copy the most significant bit (the sign bit) into the other bits 0010 -> 0000 0010 1010 -> 1111 1010 • sign extension versus zero extend (lb vs. lbu)

  8. Goal: Design an ALU for the MIPS ISA • Must support the Arithmetic/Logic operations of the ISA • Tradeoffs of cost and speed based on frequency of occurrence, hardware budget

  9. MIPS Arithmetic and Logic Instructions 31 25 20 15 5 0 • Signed arithmetic generates overflow, but no carry out R-type: op Rs Rt Rd funct I-Type: op Rs Rt Immed 16 Type op funct ADDI 001000 xx ADDIU 001001 xx SLTI 001010 xx SLTIU 001011 xx ANDI 001100 xx ORI 001101 xx XORI 001110 xx LUI 001111 xx Type op funct ADD 000000 100000 ADDU 000000 100001 SUB 000000 100010 SUBU 000000 100011 AND 000000 100100 OR 000000 100101 XOR 000000 100110 NOR 000000 100111 Type op funct 000000 101000 000000 101001 SLT 000000 101010 SLTU 000000 101011 000000 101100

  10. Addition & Subtraction • Just like in grade school (carry/borrow 1s) 0111 0111 0110+ 0110- 0110- 0101 • Two's complement operations easy • subtraction using addition of negative numbers0111  0111 - 0110+ 1010 • Overflow (result too large for finite computer word): • e.g., adding two n-bit numbers does not yield an n-bit number 0111 + 0001 1101 0001 0001 0001 1 0001 1000

  11. Building a 1-bit Binary Adder S = A xor B xor carry_in carry_out = AB v Acarry_in v Bcarry_in (majority function) carry_in A 1 bit Full Adder S B carry_out • How can we use it to build a 32-bit adder? • How can we modify it easily to build an adder/subtractor?

  12. c0=carry_in A0 1-bit FA S0 B0 c1 A1 1-bit FA S1 B1 c2 A2 1-bit FA S2 B2 c3 . . . c31 A31 1-bit FA S31 B31 c32=carry_out Building 32-bit Adder • Just connect the carry-out of the least significant bit FA to the carry-in of the next least significant bit and connect . . .

  13. add/subt c0=carry_in A0 1-bit FA S0 B0 c1 control (0=add,1=subt) A1 1-bit FA B0 if control = 0, !B0 if control = 1 S1 B0 B1 c2 A2 1-bit FA S2 B2 c3 . . . c31 A31 1-bit FA S31 B31 c32=carry_out Building 32-bit Adder/Subtractor • Remember 2’s complement is just • complement all the bits • add a 1 in the least significant bit A 0111  0111 B - 0110+ 1010

  14. Overflow Detection and Effects • Overflow: the result is too large to represent in the number of bits allocated • When adding operands with different signs, overflow cannot occur! Overflow occurs when • adding two positives yields a negative • or, adding two negatives gives a positive • or, subtract a negative from a positive gives a negative • or, subtract a positive from a negative gives a positive • On overflow, an exception (interrupt) occurs • Control jumps to predefined address for exception • Interrupted address (address of instruction causing the overflow) is saved for possible resumption • Don't always want to detect (interrupt on) overflow

  15. 0 1 1 1 1 0 0 1 1 1 7 1 1 0 0 –4 + 0 0 1 1 3 + 1 0 1 1 – 5 1 0 1 0 0 1 Overflow Detection • Overflow: the result is too large to represent in the number of bits allocated • Overflow occurs when • adding two positives yields a negative • or, adding two negatives gives a positive • or, subtract a negative from a positive gives a negative • or, subtract a positive from a negative gives a positive • On your own: Prove you can detect overflow by: • Carry into MSB xor Carry out of MSB – 6 1 1 7

  16. add/subt carry_in op AND A OR XOR result NOR B or !B 1-bit FA Mux B add/subt carry_out A Simple ALU Cell A and B A and !B A or B A or !B A xor B A xor !B A nor B A nor !B A + B A - B

  17. A and B A and !B A or B A or !B A xor B A xor !B A nor B A nor !B A + B A - B A Simple 32-bit ALU add/sub op A0 result0 B0 + A1 result1 B1 + . . . A31 result31 B31 +

  18. Tailoring the ALU to the MIPS ISA • Need to support the set-on-less-than instruction (slt) • remember: slt is an arithmetic instruction • produces a 1 if rs < rt and 0 otherwise • use subtraction: (a - b) < 0 implies a < b • Need to support test for equality (beq) • use subtraction: (a - b) = 0 implies a = b • Need to add the overflow detection hardware

  19. less Modifying the ALU Cell for slt add/subt carry_in op A result 1-bit FA B add/subt carry_out

  20. A0 result0 B0 + less A1 result1 B1 + 0 less . . . A31 result31 B31 + less 0 set Modifying the ALU for slt • First perform a subtraction • Make the result 1 if the subtraction yields a negative result • Make the result 0 if the subtraction yields a positive result • tie the most significant sum bit (sign bit) to the low order less input

  21. op zero . . . add/subt Modifying the ALU for Zero A0 • First perform subtraction • Insert additional logic to detect when all result bits are zero result0 B0 + less A1 result1 B1 + 0 less . . . A31 result31 • Note zero is a 1 when result is all zeros B31 + 0 less set

  22. 0 1 1 1 1 0 0 1 1 1 7 1 1 0 0 –4 + 0 0 1 1 3 + 1 0 1 1 – 5 1 0 1 0 0 1 Review: Overflow Detection • Overflow: the result is too large to represent in the number of bits allocated • Overflow occurs when • adding two positives yields a negative • or, adding two negatives gives a positive • or, subtract a negative from a positive gives a negative • or, subtract a positive from a negative gives a positive • On your own: Prove you can detect overflow by: • Carry into MSB xor Carry out of MSB – 6 1 1 7

  23. op overflow add/subt Modifying the ALU for Overflow A0 • Modify the most significant cell to determine overflow output setting • Disable overflow bit setting for unsigned arithmetic result0 B0 + less A1 result1 B1 zero + . . . 0 less . . . A31 result31 + B31 0 less set

  24. MULTIPLY (unsigned) • Paper and pencil example (unsigned): Multiplicand 1000Multiplier 1001 1000 0000 0000 1000 Product 01001000 • m bits x n bits = m+n bit product • Binary makes it easy: • 0 => place 0 ( 0 x multiplicand) • 1 => place a copy ( 1 x multiplicand) • 4 versions of multiply hardware & algorithm: • successive refinement

  25. 0 0 0 0 A3 A2 A1 A0 B0 A3 A2 A1 A0 B1 A3 A2 A1 A0 B2 A3 A2 A1 A0 B3 P7 P6 P5 P4 P3 P2 P1 P0 Unsigned Combinational Multiplier • Stage i accumulates A * 2 i if Bi == 1 • Q: How much hardware for 32 bit multiplier? Critical path?

  26. A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0 How does it work? 0 0 0 0 0 0 0 • at each stage shift A left ( x 2) • use next bit of B to determine whether to add in shifted multiplicand • accumulate 2n bit partial product at each stage B0 B1 B2 B3 P7 P6 P5 P4 P3 P2 P1 P0

  27. Unisigned shift-add multiplier (version 1) • 64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg, 32-bit multiplier reg Shift Left Multiplicand 64 bits Multiplier Shift Right 64-bit ALU 32 bits Write Product Control 64 bits Multiplier = datapath + control

  28. 1. Test Multiplier0 Start Multiply Algorithm Version 1 • Product Multiplier Multiplicand 0000 0000 0011 0000 0010 • 0000 0010 0001 0000 0100 • 0000 0110 0000 0000 1000 • 0000 0110 Multiplier0 = 1 Multiplier0 = 0 1a. Add multiplicand to product & place the result in Product register 2. Shift the Multiplicand register left 1 bit. 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done

  29. Observations on Multiply Version 1 • 1 clock per cycle => ­ 100 clocks per multiply • Ratio of multiply to add 5:1 to 100:1 • 1/2 bits in multiplicand always 0=> 64-bit adder is wasted • 0’s inserted in left of multiplicand as shifted=> least significant bits of product never changed once formed • Instead of shifting multiplicand to left, shift product to right?

  30. MULTIPLY HARDWARE Version 2 • 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, 32-bit Multiplier reg Multiplicand 32 bits Multiplier Shift Right 32-bit ALU 32 bits Shift Right Product Control Write 64 bits

  31. 1. Test Multiplier0 1a. Add multiplicand to the left half ofproduct & place the result in the left half ofProduct register Start Multiply Algorithm Version 2 Multiplier Multiplicand Product0011 0010 0000 0000 Multiplier0 = 1 Multiplier0 = 0 • Product Multiplier Multiplicand 0000 0000 0011 0010 2. Shift the Product register right 1 bit. 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done

  32. A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0 A3 A2 A1 A0 What’s going on? 0 0 0 0 • Multiplicand stay’s still and product moves right B0 B1 B2 B3 P7 P6 P5 P4 P3 P2 P1 P0

  33. Observations on Multiply Version 2 • Product register wastes space that exactly matches size of multiplier=> combine Multiplier register and Product register

  34. MULTIPLY HARDWARE Version 3 • 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, (0-bit Multiplier reg) Multiplicand 32 bits 32-bit ALU Shift Right Product (Multiplier) Control Write 64 bits

  35. 1. Test Product0 1a. Add multiplicand to the left half of product & place the result in the left half of Product register Start Multiply Algorithm Version 3 Multiplicand Product0010 0000 0011 Product0 = 1 Product0 = 0 2. Shift the Product register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done

  36. Observations on Multiply Version 3 • 2 steps per bit because Multiplier & Product combined • MIPS registers Hi and Lo are left and right half of Product • Gives us MIPS instruction MultU • How can you make it faster? • What about signed multiplication? • easiest solution is to make both positive & remember whether tocomplement product when done (leave out the sign bit, run for 31 steps) • apply definition of 2’s complement • need to sign-extend partial products and subtract at the end • Booth’s Algorithm is elegant way to multiply signed numbers using same hardware as before and save cycles • can handle multiple bits at a time

  37. Motivation for Booth’s Algorithm • Example 2 x 6 = 0010 x 0110: 0010 x 0110 + 0000 shift (0 in multiplier) + 0010 add (1 in multiplier) + 0100 add (1 in multiplier) + 0000 shift (0 in multiplier) 00001100 • ALU with add or subtract gets same result in more than one way: 6 = – 2 + 8 0110 = – 00010 + 01000 = 11110 + 01000 • For example • 0010 x 0110 0000 shift (0 in multiplier) – 0010 sub (first 1 in multpl.) . 0000 shift (mid string of 1s) . + 0010 add (prior step had last 1) 00001100

  38. –1 + 10000 01111 Booth’s Algorithm Current Bit Bit to the Right Explanation Example Op 1 0 Begins run of 1s 0001111000 sub 1 1 Middle of run of 1s 0001111000 none 0 1 End of run of 1s 0001111000 add 0 0 Middle of run of 0s 0001111000 none Originally for Speed (when shift was faster than add) • Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one

  39. Booths Example (2 x 7) 1a. P = P - m 1110 + 1110 1110 0111 0 shift P (sign ext) 1b. 0010 1111 00111 11 -> nop, shift 2. 0010 1111 10011 11 -> nop, shift 3. 0010 1111 11001 01 -> add 4a. 0010 + 0010 0001 11001 shift 4b. 0010 0000 1110 0 done Operation Multiplicand Product next? 0. initial value 0010 0000 0111 0 10 -> sub

  40. Booths Example (2 x -3) 1a. P = P - m 1110 + 1110 1110 1101 0 shift P (sign ext) 1b. 0010 1111 01101 01 -> add + 0010 2a. 0001 01101 shift P 2b. 0010 0000 10110 10 -> sub + 1110 3a. 0010 1110 10110 shift 3b. 0010 1111 0101 1 11 -> nop 4a 1111 0101 1 shift 4b. 0010 1111 10101 done Operation Multiplicand Product next? 0. initial value 0010 0000 1101 0 10 -> sub

  41. MIPS logical instructions Instruction Example Meaning Comment and and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical AND or or $1,$2,$3 $1 = $2 | $3 3 reg. operands; Logical OR xor xor $1,$2,$3 $1 = $2 Å $3 3 reg. operands; Logical XOR nor nor $1,$2,$3 $1 = ~($2 |$3) 3 reg. operands; Logical NOR and immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg, constant or immediate ori $1,$2,10 $1 = $2 | 10 Logical OR reg, constant xor immediate xori $1, $2,10 $1 = ~$2 &~10 Logical XOR reg, constant shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend) shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variable shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable

  42. Shifters Two kinds: logical-- value shifted in is always "0" arithmetic-- on right shifts, sign extend "0" msb lsb "0" msb lsb "0" Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted!

  43. 1 0 S2 S1 S0 A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 Combinational Shifter from MUXes B A Basic Building Block • What comes in the MSBs? • How many levels for 32-bit shifter? • What if we use 4-1 Muxes ? sel D 8-bit right shifter

  44. General Shift Right Scheme using 16 bit example S 0 (0,1) S 1 (0, 2) S 2 (0, 4) S 3 (0, 8) If added Right-to-left connections could support Rotate (not in MIPS but found in ISAs)

  45. 32 32 32 Funnel Shifter Instead Extract 32 bits of 64. • Shift A by i bits (sa= shift right amount) • Logical: Y = 0, X=A, sa=i • Arithmetic? Y = _, X=_, sa=_ • Rotate? Y = _, X=_, sa=_ • Left shifts? Y = _, X=_, sa=_ Y X Shift Right R Y X Shift Right R

  46. Barrel Shifter Technology-dependent solutions: transistor per switch SR3 SR2 SR1 SR0 D3 D2 A6 D1 A5 D0 A4 A3 A2 A1 A0

  47. Divide: Paper & Pencil 1001 Quotient Divisor 1000 1001010 Dividend–1000 10 101 1010 –1000 10 Remainder (or Modulo result) See how big a number can be subtracted, creating quotient bit on each step Binary => 1 * divisor or 0 * divisor Dividend = Quotient x Divisor + Remainder=> | Dividend | = | Quotient | + | Divisor | 3 versions of divide, successive refinement

  48. DIVIDE HARDWARE Version 1 • 64-bit Divisor reg, 64-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg Shift Right Divisor 64 bits Quotient Shift Left 64-bit ALU 32 bits Write Remainder Control 64 bits

  49. Start: Place Dividend in Remainder 1. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register. 2b. Restore the original value by adding the Divisor register to the Remainder register, & place the sum in the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0. 2a. Shift the Quotient register to the left setting the new rightmost bit to 1. 3. Shift the Divisor register right1 bit. n+1 repetition? Done Divide Algorithm Version 1 • Takes n+1 steps for n-bit Quotient & Rem. Remainder Quotient Divisor0000 01110000 0010 0000 Remainder < 0 Test Remainder Remainder  0 No: < n+1 repetitions Yes: n+1 repetitions (n = 4 here)

  50. Observations on Divide Version 1 • 1/2 bits in divisor always 0=> 1/2 of 64-bit adder is wasted => 1/2 of divisor is wasted • Instead of shifting divisor to right, shift remainder to left? • 1st step cannot produce a 1 in quotient bit (otherwise too big) => switch order to shift first and then subtract, can save 1 iteration

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