1 / 15

Width Minimization In the Single-Electron Transistor Array Synthesis

Width Minimization In the Single-Electron Transistor Array Synthesis. Speaker: Chian Wei Liu Advisor: Dr. Chun-Yao Wang 2014/01/13. OUTLINE. Motivation Width minimization approach Discussion Experimental result Future work. M otivation.

malory
Télécharger la présentation

Width Minimization In the Single-Electron Transistor Array Synthesis

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Width Minimization In the Single-Electron Transistor Array Synthesis Speaker: Chian Wei Liu Advisor: Dr. Chun-Yao Wang 2014/01/13

  2. OUTLINE • Motivation • Width minimization approach • Discussion • Experimental result • Future work

  3. Motivation • The previous work focuses on reducing the number of hexagons in SET arrays while the area is more related to the width. 1 1 -3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3

  4. Problem Formulation • Given: • A Boolean circuit and its LTG network. • Objective: • Configuring the circuit into SET arrays result in the smaller width.

  5. OUTLINE • Motivation • Width minimization approach • Discussion • Experimental result • Future work

  6. Key Idea • Reducing numbers of product terms • Architecture relaxation • In the previous work, for simplification, they allow either (high, low) or (low, high) to appear in an SET array • For width minimization, we allow both (high, low) and (low, high) to appear in an SET array • Branch-then-Share collection

  7. Width Minimization Approach • Product term computation from Threshold Networks • Branch-then-Share collection • Variable reordering • Architecture relaxation • Product term reordering

  8. OUTLINE • Motivation • Width minimization approach • Discussion • Experimental result • Future work

  9. Discussion • The tradeoff between the time and the area P1: 21001 P2: 20201 P3: 20212 P4: 21012 rechecking costs too much time

  10. Discussion • Would the ladder-shape architecture makes the width smaller ? ?

  11. OUTLINE • Motivation • Width minimization approach • Discussion • Experimental result • Future work

  12. Experimental result

  13. OUTLINE • Motivation • Width minimization approach • Discussion • Experimental result • Future work

  14. Key Idea • Reducing numbers of product terms • Architecture relaxation • Branch-then-Share collection creation

  15. Future work • Reordering variables according to the feature of the Branch-then-Share to creature more Branch-the-Share • If the EBL is not meaningful of width minimization, the product term reordering should make down the priority of the EBL • Proposing a new method of enhance expansion focusing on width minimization • Remap the nodes if the expansion occurs at the middle of the array

More Related