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D1600 PowerSense3 Semicustom Array

D1600 PowerSense3 Semicustom Array. ELE 535 BiCMOS Design University of Rhode Island. D1600 PowerSense3 Semicustom Array. Agenda Introduce You to the IC for Your Projects Component Availability - Limitations Device Characteristic Basics

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D1600 PowerSense3 Semicustom Array

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  1. D1600 PowerSense3 Semicustom Array ELE 535 BiCMOS Design University of Rhode Island

  2. D1600 PowerSense3 Semicustom Array Agenda • Introduce You to the IC for Your Projects • Component Availability - Limitations • Device Characteristic Basics • Design Considerations for your Projects on this Array • Intro to Layout Considerations • Discussion on Project Selection • and a few suggestions (pet projects) • Q & A

  3. D1600 Array Summary • 30,000 mil2 Die • 52 Bond Pads • - (protected) • Bandgap Reg • - (w/ 5 bit trim) • Charge Pump • 756 Logic Gates • 1200 MOS • 400 Bipolar • 43 DMOS • 9 MΩ Res. • 400 pF Cap

  4. Charge Pump Mixed Analog BCD LV MOS OpAmp Switch cap OpAmp A LOGIC CORE Analog Mix A LV BiC A LV MOS Bias Bandgap D1600 Blocks • 15 Blocks • ChargePump • Bandgap • 2 x OpAmp • SwitchCap • Bias • 4 x Mixed BCD • 4 Misc Analog • Logic Core • +15 Logic I/O cells

  5. Mixed Analog BCD Block • 29 NPN • 31 PNP • 62 NMOS • 84 PMOS • 7 DMOS • 1.3 MΩ resistance • 40 pF capacitance

  6. Mixed Analog Block – Detail Component Count

  7. ON Semiconductor: Add Bigger picture of Block here, and list the considerations on a separate slide. Mention matching of R’s and xistors, DLM, metal width and pitch, via size, current carrying capability, Metal resistance and drop, selecting devices for breakdown V, tub Biasing etc. Maybe need follow-up lecture, cover design issues here, and layout issues in follow-up! Design Considerations • Device Availability • - Bipolar vs MOS, LV vs HV, Resistor types, etc • - Location / Accessibility of Devices • Breakdown Voltages • - C-E, E-B, D-S, G-B... • Device Matching • Resistors:expect BEST CASE 1% using matched strings • :unmatched strings – SIGNIFICANTLY worse • Bipolar : 1mV with care in layout • MOS: Order of magnitude worse than Bipolar • Temperature Coefficient • - See PSPICE models

  8. Device (W/L) Parameter (unit) target min max Device (W/L) Parameter Target Min Max HVP (80/13 udr) Double sided MVN (40/8 udr) Vt (v) Vt (v) -1.55 2.0 -1.15 1.6 -1.95 2.4 Gm (u-mho) Gm (u-mho) 7.9 17.6 5.3 13.2 22.0 10.6 LVN (40/4 udr) Vt (v) 1.0 0.7 1.3 Id (ma) Id (ma) Gm (u-mho) 74 53 95 Lk (amp) Lk (amp) Id (ma) Bv (v) Bv (v) 23 -100.0 18 -80.0 -- -- Lk (amp) Bv (v) 13 7 -- MVP(40/11udr) Vt (v) -1.6 -1.3 -2.0 Gm (u-mho) 5.29 2.64 7.93 LVP (40/4 udr) Vt (v) -1.1 -0.7 -1.5 Id (ma) Gm (u-mho) 31 17.6 39.6 Lk (amp) Id (ma) Bv (v) -40.0 -30.0 -- Lk (amp) Bv (v) -14.0 -7.0 -- Device Performance - MOS Transistors Note: 1.Vt is the line interception of Id / Vg at maximum slope where Vd = 0.1v. 2.Gm is the maximum slope of Id / Vg. 3.Id is at Vg = Vd = 5v. 4.Leakage is at Vg = 0v, and Vd = 5v. 5.Bv is at Id = 50 ua.

  9. Device (area) Parameter (unit) Mean sigma Note: Small DMOS with Pwell edge termination (21 cell) Vt (v) 1.84 0.075 Vd = 0.1 v Bv (v) 84.4 4.25 Id = 50 ua Lk (amp) < 20 na Vg = 0v, Vd = 5v Rdson (Vd / Id) 36.6 4.12 Vd @ Vg = 10v & Id = 10ma Rdson @.2v (Vd/Id) 35.9 3.05 Id @ Vg = 10v & Vd = 0.2v Device Performance - DMOS Note: 1.Vt is the line interception of Id / Vg at maximum slope where Vd = 0.1v. 2.Bv is at Id = 50 ua. 3.Leakage is at Vg = 0v, and Vd = 5v. 4.Rdson is the ratio of Vd / Id at Vg = 10v & Id = 10ma. Rdson @.2v is the ratio of Vd / Id at Vg = 10v & Vd = 0.2v.

  10. Device type Min BVdss Max operation V Vgs Estimated specific Rdson (mohm-cm2) LVNMOS 7v 5.5v 5v 1.0 MVNMOS 18v 16.5v 10v 4.5 LVPMOS -7v -5.5v -5v 2.5 MVPMOS -30v -16.5v -10v 12.5 HVPMOS -80v -65v -10v 60 N-VDMOS 65V 65v 65v 10v 3.6 Device Performance – MOS Specific Rdson (at 25°C)

  11. Device Parameters(unit) Target min max Lateral PNP NHV - NPN Beta @50u Beta @50u 140 25.0 10.0 70 40.0 300 Vbe (v) Vbe (v) 0.658 0.670 Vsat @ 200u (v) Vsat @ 200u (v) 0.1 0.15 Bvceo (v) Bvceo (v) 55.0 30.0 40.0 20.0 -- -- Bvcbo (v) Bvcbo (v) 60.0 60.0 35.0 40.0 -- -- Bvebo (v) Bvebo (v) 70.0 30.0 22.0 45.0 38.0 -- Substrate PNP Beta @50u 40.0 25.0 70.0 Vbe (v) 0.672 Vsat @ 200u (v) 0.20 Bvceo (v) 40.0 20.0 -- Bvcbo (v) 70.0 45.0 -- Bvebo (v) 70.0 45.0 -- Device Performance - Bipolar Note: 1.Beta @50u is the transistor beta measured at Ic = 50 ua. 2.Vbe is measured at Ic + Ib = 10 ua. 3.Vsat @ 200u is the Vce measured at Ic = 200 ua. 4.Bvceo, Bvcbo, Bvebo at I = 10 ua.

  12. Junctions Zeners Target Target Min Min Max Max BL / Iso Bl / Sub 100.0 10.0 8.5 70 -- -- Nsd / Iso (7 udr)* Nsd / Pwell 17.5 5.2 4.8 15 5.6 -- Nsd / Iso (9 udr) Nhv / Pwell 5.6 45.0 5.2 35 -- 6.0 Psd / Epi Nsd / Psd(in Pwell) Min 30.0 5.8 5.3 22 -- 6.3 Nsd / Phv(in Pwell) Phv / Epi 70.0 10.5 9.0 55 12.0 -- Nsd / Pwell Nsd / Phv 19.6 11.0 9 17.5 -- 21.7 Nsd / Hfb(in Pwell) Nsd / Psd (in Pwell) 6.0 5.8 5.0 5.3 -- 7.0 Pwell / Epi w/o Bl 110.0 90 -- Pwell / Epi w/ Bl 105.0 80 -- Device Performance – Junction Breakdowns

  13. Device Absolute deviation Matching % 6 um 12 um 30 um 6 um 12 um 30 um Poly1 26.6 % 19.3 % 14.3 % 1.0 % 0.8 % 0.50 % Poly2 26.5 % 23.7 % 24.4 % 1.3 % 0.9 % 0.60 % PHV 24.0 % 21.6 % 21.5 % 0.8 % 0.22 % 0.20 % PSD 17.6 % 13.4 % 10.8 % 0.15 % 0.10 % 0.08 % NHV 46.3 % 41.9 % 39.9 % 0.3 % 0.17 % -- NSD 20.1 % 18.5 % 14.8 % 0.15 % 0.1 % -- Pwell 21.8 % 15.9 % 16.4 % -- 0.4 % 0.36 % Device Performance – Resistors

  14. ON Semiconductor: Add Bigger picture of Block here, and list the considerations on a separate slide. Mention matching of R’s and xistors, DLM, metal width and pitch, via size, current carrying capability, Metal resistance and drop, selecting devices for breakdown V, tub Biasing etc. Maybe need follow-up lecture, cover design issues here, and layout issues in follow-up! Layout Considerations • Device Matching • - Proximity and orientation • - Use identical strings for Resistor matches • Tub Bias • - N-Tubs to Most + V used in tub, P-Tubs to most -. • Metal Rules and Runs • Dual Level Metal • M1: 4udr width, 4udr space, 1.75mA/udr, 0.052Ω/sq max • M2: 18udr width, 18udr space, 3.5mA/udr, 0.02Ω/sq max • Must consider current carrying capability and Vdrops • Temperature Coefficient • - See PSPICE models

  15. ON Semiconductor: Add Bigger picture of Block here, and list the considerations on a separate slide. Mention matching of R’s and xistors, DLM, metal width and pitch, via size, current carrying capability, Metal resistance and drop, selecting devices for breakdown V, tub Biasing etc. Maybe need follow-up lecture, cover design issues here, and layout issues in follow-up! Open Discussion • Projects • -- Complexity • Samples • Pet Projects • Q & A

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