An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications

1. An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications Guohe Yin, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Zhihua Wang Macau University

2. 1. Introduction to SAR ADC 2. Proposed ADC Architecture 3. Circuit Implementation 4. Simulation Results 5. Conclusions Outline 2014/9/12 2

3. 1.The SAR ADC Advantages: Low power; Simple architecture; Middle area; Disadvantages: The capacitor ratio increase extremely with the resolution. So, for the 10-bit ADC, the MSB capacitor is 512C!! 10 bit charge redistribution SAR ADC

4. 2. Proposed ADC Architecture The proposed 9-bit two-stage pipelined ADC architecture 2014/9/12 4

5. 2. Proposed ADC Architecture Timing diagram of pipelined SAR ADC 2014/9/12 5

6. 3. Switch scheme Advantages: MSB capacitor 16C, not 512C; No op-amp; Capacitive DAC arrays of the 10-bit pipelined SAR ADC 2014/9/12 6

7. 3. Switch scheme Not Vcm!! Circuit diagram of MSB and LSB DAC arrays in sharing phase 2014/9/12 7

8. 3. Switch scheme The output voltage of the DAC array: Before sharing phase, MSB-array voltage: After sharing phase, LSB-array voltage: 2014/9/12 8

9. 3. Switch scheme MSB and LSB DAC arrays in sharing phase with determined LSB reference voltage 2014/9/12 9

10. 4. Circuit Implementation 4.1 The comparator The Dynamic latch with Pre-amplifier gain 16. 2014/9/12 10

11. 4. Circuit Implementation 4.2 Digital Error Correction To eliminate the offset of two comparators, the last bit of coarse and the first bit of the fine stage are combined into one bit for overlapping. 4.3 Successive Approximation Register (SAR) In this ADC, only 6-DFFs instead of 11 in SAR ADC, low digital power. 4.4 Reference Ladder Resistor/tap = 1.6 K Ohm Unit capacitance =16 fF for the DAC Array 2014/9/12 11

12. 5. Simulation Result The static performance DNL (differential nonlinearity): +0.46/-0.66 LSB INL (integral nonlinearity) : +0.37/-0.53 LSB Fig.9 Simulated DNL and INL 2014/9/12 12

13. 5. Simulation Result Fig.10. FFT of the digital output @ fin=403.3 kHz and fS =1 MS/s. Fig.11. Histogram of SNDR of proposed novel ADC @ fin =484.4 KHz and fS =1 MS/s. Fig.12. Simulated SNDR versus input frequency @ fS =1 MS/s. Fig.13. Simulated SNDR versus sampling rate. 2014/9/12 13

14. Performance table 2014/9/12 14

15. References 1. X. Zou, X. Xu, L. Yao, Y. Lian, “ A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip,” IEEE J. Solid State Circuits, vol. 44, no.4, pp. 1067 - 1077, Apr. 2009. 2. C. Liu, S. Chang, G. Huang, Yi. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. Solid State Circuits, vol. 45, no.4, pp. 731 – 740, Apr. 2010. 3. A. M. Abo, P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipelined analog-to-digital converter,” IEEE J. Solid State Circuits, vol. 34, no. 5, pp. 599-606, May 1999. 4. M. V. Elzakker, V. E. Tuijl , P. Geraedts, D. Schinkel, E. Klumperink, B. Nauta, “A 10-bit Charge-Redistribution ADC Consuming 1.9 uW at 1 MS/s,” IEEE J. Solid State Circuits, vol. 45, no.5, pp. 1007 – 1015, May 2010. 5. G. Y. Huang, C. C. Liu; Y. Z. Lin, S. J. Chang, "A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance," Procs. IEEE ASSCC, pp. 157 - 160, Dec. 2009. 6. J. Craninckx, G. van der Plas, “A 65 fJ/conversion-step 0-to-50 MS/s 0-to-0.7 mW 9 b charge-sharing SAR ADC in 90 nm digital CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 246–247, Feb. 2007.

16. Conclusions A 9-bit 1 MS/s SAR ADC with pipelined architecture is presented: 1) Reduce the digital power 2) The total capacitance is 2*32C instead of 512C; 3) No operational amplifier The ADC consumes power 10.26 μW, and achieves the FOM 28.3 fJ/conversion-step. 2014/9/12 16

17. Thank you!