Download
low power design on soc n.
Skip this Video
Loading SlideShow in 5 Seconds..
Low Power Design on SoC PowerPoint Presentation
Download Presentation
Low Power Design on SoC

Low Power Design on SoC

195 Vues Download Presentation
Télécharger la présentation

Low Power Design on SoC

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

  1. Low Power Design on SoC Member : 張民杰 P90921010 郭光爵 P91921004 黃興洋 R91922047 Speaker : 郭光爵

  2. Outline • Why Low Power ? • Design Issues on Power Consumption • Key Criteria for Power Reduction • General Approaches • Conclusion

  3. Outline • Why Low Power ? • Design Issues on Power Consumption • Key Criteria for Power Reduction • General Approaches • Conclusion

  4. Motivation of Low Power • Energy-efficient computing is required by • Mobile electronic systems • Large-scale electronic systems • Requirement of energy efficiency affects all aspects of system design • Packaging costs • Cooling costs • Power supply rail design • Noise immunity and system reliability

  5. Technology Directions

  6. Chip Power Densities

  7. Outline • Why Low Power ? • Design Issues on Power Consumption • Key Criteria for Power Reduction • General Approaches • Conclusion

  8. Basic Concepts (1/2) • P = CLVDD2f 01 + tsc VDD Ipeak f 0  1 + VDD Ipeak • Dynamic term (~90%) CLVDD2f 01 • Short-circuit term (~8%) tsc VDD Ipeakf 0  1 • Leakage term (~2%) VDD Ipeak • Dynamic Power • Power dissipation due to capacitance charging at transitions from 0  1 and 1  0

  9. Basic Concepts (2/2) • Short-Circuit Power • Power consumption due to brief short-circuit current during transitions • Static Power • Steady, per-cycle energy cost, e.g. Leakage Power • More important issue in deep submicron • Mostly focus on dynamic, but recently work on others

  10. Hierarchical Design (1/2)

  11. Hierarchical Design (2/2)

  12. Outline • Why Low Power ? • Design Issues on Power Consumption • Key Criteria for Power Reduction • General Approaches • Conclusion

  13. Voltage Supply (Vdd) • Biggest impact : 50% reduction in Vdd, 75% reduction in power • Can not be reduced indefinitely (can’t be too close to Vt – lower Vt means higher leakage power – and lower Vdd increases latency) • Power-driven voltage scaling • Pipelining, Parallelization, Loop unrolling • Multiple voltages • Slow down non-critical path with lower voltage supply • Two or more power grids

  14. Clock Frequency (fclk) • Has significant impact only in conjunction with Vdd scaling • Lowering only f does not decrease energy • But it may increase battery life • Reduce average power • Energy throughput becomes worse • Multi-frequency clocks

  15. Load Capacitance (CL) • Roughly proportional to the chip area • Can be reduced by re-synthesis or re-design for low power • Reduce wiring capacitance • Reduce local loads • Reduce global interconnect • Global interconnect can be reduce by improving spatial locality : trade off communication for computation

  16. Switching Activity (f01) • Very data depedent • A big portion due to glitches (real-delay) – reducing glitches • Can be reduced by power sensitive data encoding, re-synthesis (e.g. balanced designs) • Improve correlation between consecutive input to functional macros • Synergistic high-level-synthesis approaches lead best results

  17. Outline • Why Low Power ? • Design Issues on Power Consumption • Key Criteria for Power Reduction • General Approaches • Conclusion

  18. Power Estimation (1/3) • Gate level – challenges • Need node-by-node accuracy • Vdd, fclk, CL are known • Actually, layout will determine the interconnect capacitance • Need to estimate switching activity accurately • Spatial and temporal dependencies – circuit and input included

  19. Power Estimation (2/3) • RT/Microarchitectural level – challenges • Details of IP core implementation is largely unknown • Have to abstract switching activity and capacitance values • Less accurate, but more efficient • Efficient design space exploration

  20. Power Estimation (3/3) • Software and system level – challenges • Very few implementation details available • Need to rely on accurate lower level estimation tools • Complexity can be prohibitive for highly accurate estimates

  21. SimplePower SystemFramework

  22. SimplePower Compilation Framework

  23. Other Related Tools • Intel Tempest • Princeton Wattch • IBM PowerTimer

  24. Power Optimization (1/4) • Gate level • Mostly targets CL and switching activity reduction • Reduce power via • Logic synthesis • Precomputation / guarded evaluation • Clock gating

  25. Power Optimization (2/4) • RT/Behavioral/Microarchitecture level • Mostly targets CL, switching activity, as well as joint Vdd/fclk reduction • Need to rely on high-level (maybe not so accurate) estimates • Low power register sharing • Low power module assignment • Multiple supply voltage assignment • Bus encoding

  26. Power Optimization (3/4) • Software level • Per-instruction cost, plus inter-instruction effects • Ep = Σ (Bi x Ni) + Σ(Oi,j x Ni,j) + Σ Ek • Modified list scheduling algorithm for low power instruction scheduling • Operation packing • Operand swapping

  27. Power Optimization (4/4) • System level • Platform-based design • Workload specific mapping • Application and platform modeling and mapping • Dynamic power management • Operating System – driven • Microarchitecture and Software supported • ACPI, DPM • “Energy Aware Computing” • Yung-Hsiang Lu, Luca Benini, Member, IEEE and Giovanni De Micheli, Fellow, IEEE Power-Aware Operating Systems for Interactive System, IEEE Trans. on VLSI