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Low Power Design Techniques

Low Power Design Techniques. Lecture. Dr.Ing . Goran Panić. 1 9. 05 .201 6. Fakultet Tehni čkih Nauka, Čačak. Agenda. 1. 2. 3. 4. 5. 6. 7. Introduction. Power Consumption. Standard Low Power Techniques. Advanced Low Power Techniques. Power Aware Design Methodologies.

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Low Power Design Techniques

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  1. Low Power Design Techniques Lecture Dr.Ing. Goran Panić 19.05.2016 FakultetTehničkih Nauka, Čačak

  2. Agenda 1 2 3 4 5 6 7 Introduction Power Consumption Standard Low Power Techniques Advanced Low Power Techniques Power Aware Design Methodologies Future Trends In Low Power Design Conclusion

  3. Agenda 1 2 3 4 5 6 7 Introduction Power Consumption Standard Low Power Techniques Advanced Low Power Techniques Power Aware Design Methodologies Future Trends in Low Power Design Conslusion

  4. Why Low Power? • more functionality, limited battery capacity

  5. Introduction – Bulk-CMOS Trends • CMOS Scaling – Increase of static power loss Low Power Design – Advancedtechniquestoreducebothstaticanddynamic power

  6. Introduction – Advanced CMOS Trends • New Process Technologies - SOI, Multi-gate, FinFet, etc. Source: ITRS 2011 Reduced Static Power - still needs to be maintained!

  7. Agenda 2 1 3 4 5 6 7 Power Consumption Introduction Standard Low Power Techniques Advanced Low Power Techniques Power Aware Design Methodologies Future Trends in Low Power Design Conclusion

  8. Power Consumption – Power vs Energy • Energy determines the battery life! E1 = P x T E2 = (P/2) x 2T = P x T = E1

  9. Power Consumption – Power in CMOS • CMOS Power = Dynamic Power + Static Power Dynamic Power - power dissipationwhenlogicgatesareswitching - associatedwithactivemodeofoperation - consistsoftwocomponents: switchingand internal power Static Power - resultsfromleakagecurrents - dissipated also whentransistorsareturned off - inreaseswithdeviceshrinking, i.e. technologyscaling

  10. Power Consumption – Dynamic Power Loss • Switching Power – power consumption due tocharge/dischargeofloadcapacitance

  11. Power Consumption – Dynamic Power Loss • Internal Power – short-circuit power wheninputsignalis at intermediate voltagelevel

  12. Power Consumption - Static Power Loss • I1 - reverse-bias p-n junction diode leakage • I2 - subthreshold leakage • I3 - gate leakage through the oxide • I4 - gate induced drain leakage Static Power – Leakage power resulting from leaking currents in transistors

  13. Agenda 3 1 2 4 5 6 7 Standard Low Power Techniques Introduction Power Consumption Advanced Low Power Techniques Power Aware Design Methodologies Future Trends in Low Power Design Conclusion

  14. Standard Low Power Techniques • Established for mature technologies • Focused on reducing supply voltage, switching activity and load capacitance Standard Low Power Techniques: Supply voltagescaling (multi-Vdd) Multi-thresholdvoltage Clockgating Operand isolation Gate-level optimization

  15. Standard Low Power Techniques – Multi-Vdd • different blocks operate at different supply voltage • benefits from reduction of supply voltage large impact on design complexity

  16. Standard Low Power Techniques – Multi-Vth • usage of both high-Vth and low-Vth transistors in a single chip • high impact on static power • moderate impact on dynamic power • implementation supported by EDA tools

  17. Standard Low Power Techniques – Clock Gating • mostpopularstandardtechnique • disablingtheswitchingofclocknets in inactivepartsofcircuit significantreductionofswitching power automaticclockgatinginsertionsupportedby EDA tools

  18. Standard Low Power Techniques – Operand Isolation • similartoclockgating • reducesswitchingactivity in inactive datapath blocks • automatized implementation supported by modern EDA tools

  19. high activity net high power input low activity net low activity net high activity net low power input high activity net Standard Low Power Techniques – Gate Level Optimization • logic restructuring – making high-activity nets internal to the cell • pin swapping – rewiring of low-capacitance gate pins to high-activity nets • other gate-level techniques: cell sizing, buffer insertion

  20. Standard Low Power Techniques - Overview • Dynamic Power – multi-Vdd and clock gating most effective • Static Power – multi-Vth and multi-Vdd most effective • Implementation automated (except for multi-Vdd)

  21. Agenda 4 1 2 3 5 6 7 Advanced Low Power Techniques Introduction Power Consumption Standard Low Power Techniques Power Aware Design Methodologies Future Trends in Low Power Design Conclusion

  22. Advanced Low Power Techniques • Developed to deal with the increasing contribution of leakage currents in deep-submicron CMOS Process-Level Techniques: Retrograde andhalodoping (bulk-CMOS) Silicon-On-Insulator (SOI) Multiple-Gate MOSFET (FinFet) Circuit-Level Techniques: Multi-voltage design Voltageandfrequencyscaling Power gating Body biasing Stackedtransistor

  23. Advanced Low Power Techniques – Retrograde and Halo Doping • Different aspects of well engineering Retrograde channeldoping - lowsurfacechannelconcentrationfollowedby a highly-dopedsubsurfaceregion - improvesshort-channeleffects, increasesurfacechannelmobility -> increaseoftresholdvoltage Halo doping - introduceshighlydoped p-regions at theedgesofthechannel - reduceswidthofdepletionarea in drainandsource -> reduceofthresholdvoltagedegradation

  24. Advanced Low Power Techniques - SOI • Bulk vs SOI Bulk-CMOS vs PDSOI vs FDSOI

  25. Advanced Low Power Techniques – Multiple-Gate MOSFET • three-dimensional multiple gates (two-gate, three-gate, allaround, etc.) • eitherbulkor SOI process FinFET Structure – three-gate MOSFET siliconfincontrolledfromthreesides -> improved subthreshold slope-> lower power in subthreshold region inversionareaincreased -> high drivecurrent -> betterperformance

  26. Advanced Low Power Design – Multi-Voltage Design Conceptof power islands (voltageislands, power domains) • SVS – staticvoltagescaling • MVS – multi-voltagescaling • DFVS – dynamicfrequencyandvoltagescaling • AFVS – adaptive voltagescaling

  27. Advanced Low Power Techniques - DFVS Benefits: reductionofbothdynamicandstatic power Challenges: voltageregulators, taskscheduling, transition time, voltageshifters, timing/voltagepairs, libraries, power-upsequencing

  28. Advanced Low Power Techniques - Power Gating (1) • Shut down the power supplyofinactiveblocks • Multithreshold-CMOS (MTCMOS) – high-Vthswitchtransistorsvslow-Vthlogic

  29. Advanced Low Power Techniques – Power Gating (2) Power gates – header vs footer Power gating controller – control of power-up sequences lsolation logic – prevents crowbar currents in active logic blocks

  30. Advanced Low Power Techniques – Power Gating (3) • Power Switches Ring vs Grid-Style

  31. Advanced Low Power Techniques – Power Gating (4) • Benefits: • large impact on static power saving • EDA tools support for automatized insertion • Challenges: • design strategy (header vs footer, fine vs coarse, ring vs column, etc) • data retention (retention flip-flops, scan-based approach, etc) • design issues (control, isolation, design flow, etc) • implementation issues (synthesis, floorplanning, etc) • testability (scan insertion, etc) • verification (functionality, power, etc)

  32. Advanced Low Power Techniques – Body Biasing • control of threshold voltage by connecting body of transistor to a bias network RBB (reverse BB) – negative body-to-sourcevoltageto NMOS (increasethreshold -> reduceleakage) FBB (forward BB) – positive body-to-soucevoltageto NMOS (decresethreshold -> bustperformance) ABB (adaptive BB) – allowscalibrationofeachchip in post-productionphase (compensationfor PVT variations) DBB (dynamic BB) – dynamicchangeofbodybiasduringchipoperation

  33. Advanced Low Power Techniques – Stacked Transistors • Stacking effect – subthershold current flowing through a series of transistors reduces when more than one transistors in the stack is turned off - reduces significantly subtheshold leakage - large area penalty

  34. Low Power Memories • Standard SRAM (MOSFET-based) • power gatingwithretention • multi-bank memories • voltagescaling • Non-Volatile RAM • Magnetoresistive RAM (MRAM) - fast Rd/Wr, unlimitedendurance, high power forwriting, scalabilityissues • Feroelectric RAM (FRAM) –goodperformance, high on/off currentratio (low power), reliabilityissues, lowdensity • Phase Change RAM (PCRAM) – goodscalability, fast, high currentforprogramming, limited numberofwritecycles, temperatureinstability • Resistive RAM (RRAM) – lowprogrammingcurrent, lowendurance

  35. Advanced Low Power Techniques - Overview • SVS/MVS – bothdynamicandstatic power savings, medium impact on architecture • DVFS – high dynamic power savings, static power savings, high impact on architecture • Power Gating– high static power savings, high impact on architecture • Body-biasing– overshadowedby power gating

  36. Agenda 5 1 2 3 4 6 7 Power Aware Design Methodologies Introduction Power Consumption Standard Low Power Techniques Advanced Low Power Techniques Future Trends in Low Power Design Conclusion

  37. Power-Aware Design Methodologies (1) • industry enabled power-aware design flows • need to express power-related specification and rules: design power intent • CPF (common power format) vs UPF (unified power format) CPF-enabled Low Power flow with Cadence tools

  38. Power-Aware Design Methodologies (2) • UPF-Enabled Synopsys Low Power Flow

  39. Power-Aware Design Methodologies (3) • High-Level Power Estimation • architecture, behavioral, instructionandsystemlevel • analyticalorempiricalmodels Comercialtools CadenceInCyte – IP based Power Theater / Power Artist – RTL level

  40. Agenda 6 1 2 3 4 5 7 Future Trends in Low Power Design Introduction Power Consumption Standard Low Power Techniques Advanced Low Power Techniques Power Aware Design Methodologies Conclusion

  41. Future Trends in Low Power Design (1) • Diversification – non-digital functionalities do not scale at same rate as CMOS Source: ITRS • trade-off between performance and power for individual applications

  42. Future Trends in Low Power Design (2) • Evolving role of design phases in system power minimization Source: ITRS • high-level methods for saving power become more important

  43. Future Trends in Low Power Design (3) • Impact of future design technology improvements on power Source: ITRS

  44. Agenda 7 1 2 3 4 5 6 Conclusion Introduction Power Consumption Standard Low Power Techniques Advanced Low Power Techniques Power Aware Design Methodologies Future Trends in Low Power design

  45. Conclusion • Power isthemostimportantchallenge in design of portable SoC design • Bothdynamicandstatic power concerned • Focus on energyreductionratherthan on peak power • Combinationofstandardandadvancedtechniquesfor optimal results • Evolveofadvancedprocesstechnologiesfocused on low power • Advanced design methodologiesforefficientlow power design • Future trendsforseemajorutilizationof high-level techniquesforsaving power • The quest forlow power continues!

  46. Goran Panić 570 671 A11B

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