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Low Power Design in VLSI

Low Power Design in VLSI. Presented by: Nitin Prakash sharma M.Tech IInd Yr. (I.T.) School of I.T. IIT Kharagpur. Content. Why low power ? Sources of power dissipation. Degrees of freedom. Issues. Challenges. References. Why Low Power ?. Growth of battery-powered systems

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Low Power Design in VLSI

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  1. Low Power Design in VLSI • Presented by: • Nitin Prakash sharma • M.Tech IInd Yr. (I.T.) • School of I.T. • IIT Kharagpur

  2. Content • Why low power ? • Sources of power dissipation. • Degrees of freedom. • Issues. • Challenges. • References. Low power design in VLSI

  3. Why Low Power ? • Growth of battery-powered systems • Users need for: • Mobility • Portability • Reliability • Cost • Environmental effects Low power design in VLSI

  4. Sources of Power Dissipation • Dynamic power dissipations: whenever the logic level changes at different points in the circuit because of the change in the input signals the dynamic power dissipation occurs. • Switching power dissipation. • Short-circuit power dissipation. • Static power dissipations: this is a type of dissipation, which does not have any effect of level change in the input and output. • Leakage power. Low power design in VLSI

  5. Switching Power Dissipation • Caused by the charging and discharging of the node capacitance. Figure 1: Switching power dissipation [1]. Low power design in VLSI

  6. Switching Power Dissipation (Contd.) • Ps/w= 0.5 *  * CL* Vdd2 * fclk • CL physical capacitance, Vdd supply voltage,  switching activity, fclk clock frequency. • CL(i) = Σj CINj + Cwire + Cpar(i) • CIN the gate input capacitance, Cwire the parasitic interconnect and Cpar diffusion capacitances of each gate[I]. • Depends on: • Supply voltage • Physical Capacitance • Switching activity Low power design in VLSI

  7. Short circuit power dissipation • Caused by simultaneous conduction of n and p blocks. Figure 2: Short circuit current [2] Low power design in VLSI

  8. Short circuit power dissipation (contd.) • Where k = (kn = kp), the trans conductance of the transistor, τ = (trise = tfall), the input/output transition time, VDD = supply voltage,f = clock frequency, and VT = (VTn = |VTp|), the threshold voltage of MOSFET. • Depends on : • The input ramp • Load • The transistor size of the gate • Supply voltage • Frequency • Threshold voltage. Low power design in VLSI

  9. Leakage power dissipation • Six short-channel leakage mechanisms are there: • I1 Reverse-bias p-n junction leakage • I2 Sub threshold leakage • I3 Oxide tunneling current • I4 Gate current due to hot-carrier injection • I5 GIDL (Gate Induced Drain Leakage) • I6 Channel punch through current • I1 and I2 are the dominant leakage mechanisms Low power design in VLSI

  10. Leakage power dissipation (contd.) Figure 3: Summary of leakage current mechanism [2] Low power design in VLSI

  11. PN Junction reverse bias current • The reverse biasing of p-n junction cause reverse bias current • Caused by diffusion/drift of minority carrier near the edge of the depletion region. where Vbias= the reverse bias voltage across the p-n junction, Js= the reverse saturation current density and A = the junction area. Low power design in VLSI

  12. Sub Threshold Leakage Current • Caused when the gate voltage is below Vth. Fig 5: Subthreshold leakage in a negative-channel metal–oxide–semiconductor (NMOS) transistor.[2] Fig 4: Sub threshold current[2] Low power design in VLSI

  13. Contribution of Different Power Dissipation Fig 6: Contribution of different powers[1] Fig 7:Static power increases with shrinking device geometries [7]. Low power design in VLSI

  14. Degrees of Freedom • The three degrees of freedom are: • Supply Voltage • Switching Activity • Physical capacitance Low power design in VLSI

  15. Supply Voltage Scaling • Switching and short circuit power are proportional to the square of the supply voltage. • But the delay is proportional to the supply voltage. So, the decrease in supply voltage will results in slower system. • Threshold voltage can be scaled down to get the same performance, but it may increase the concern about the leakage current and noise margin. Low power design in VLSI

  16. Supply Voltage Scaling (contd.) Fig 8: Scaling supply and threshold voltages [4] Fig 9: Scaling of threshold voltage on leakage power and delay[4] Low power design in VLSI

  17. Switching Activity Reduction • Two components: • f: The average periodicity of data arrivals • α: how many transitions each arrival will generate. • There will be no net benefits by Reducing f. • α can be reduced by algorithmic optimization, by architecture optimization, by proper choice of logic topology and by logic-level optimization. Low power design in VLSI

  18. Physical capacitance reduction • Physical capacitance in a circuit consists of three components: • The output node capacitance (CL). • The input capacitance (Cin) of the driven gates. • The total interconnect capacitance (Cint). • Smaller the size of a device, smaller is CL. • The gate area of each transistor determines Cin. • Cint is determine by width and thickness of the metal/oxide layers with which the interconnect line is made of, and capacitances between layers around the interconnect lines. Low power design in VLSI

  19. Issues • Technology Scaling • Capacitance per node reduces by 30% • Electrical nodes increase by 2X • Die size grows by 14% (Moore’s Law) • Supply voltage reduces by 15% • And frequency increases by 2X This will increase the active power by 2.7X Low power design in VLSI

  20. Issues (contd.) • To meet frequency demand Vt will be scaled, resulting high leakage power. *Source: Intel Fig 10:Total power consumption of a microprocessor following Moore’s Law Low power design in VLSI

  21. Some Transistor Characteristics *[MT Bhor2002] Low power design in VLSI

  22. Challenges • Development of low Vt, supply voltage and design technique • Low power interconnect and reduced activity approaches • Low-power system synchronization • Dynamic power-management techniques • Development of application-specific processing • Self-adjusting and adaptive circuits • Integrated design methodology • Power-conscious techniques and tools development • Severe supply fluctuations or current spikes and many more…………….. Low power design in VLSI

  23. References • L. Wei, K. Roy, and V. De, “Low-voltagelow-powerCMOSdesigntechniques for deep submicron ICs,” in Int. Conf. VLSI Design, Jan. 2000, pp. 24-29. • K. Roy, S. Mukhopadhyay, and H. Mahmoodi, “Leakagecurrentmechanismsandleakage reduction techniques in deep-submicron CMOS circuits”, IEEE, 2004, pp 305-327. • AP Chandrakasan and S. Sheng and RW Brodersen, “Low-PowerCMOSDigitalDesign”, JSSC, V27, N4, April 1992, pp 473--484. • Massoud Pedram, “Power minimization in IC design: principles and applications”, ACM, January 1996. • S.Borkar, “LowPowerDesignChallengesforthe decade”, Proceedings of the ASP-DAC, 2001 pp. 293-296. • MT Bohr, “Nanotechnologygoalsandchallenges for electronic applications,” IEEE Trans. Nanotechnol., vol. 1, pp. 56-62, Mar. 2002. • Nam Sung Kim, Todd Austin, David. Blaauw, Trevor Mudge, Krisztián,“Moore’s Law Meets Static Power”, Computer, December 2003, IEEE Computer Society, pp68-75. • http://en.wikipedia.org/ Low power design in VLSI

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