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Low Power SRAM VLSI Final Presentation

Low Power SRAM VLSI Final Presentation. Stephen Durant Ryan Kruba Matt Restivo Voravit Vorapitat. High Level Architecture. ADDR. 5:32 Block Enable. SRAM Block. OUT. Block I/O. SRAM Block. READ. WRITE. ADDR. OUT. DATA. BLK ENABLE. Output Buffering. SRAM Block. BLK_EN0.

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Low Power SRAM VLSI Final Presentation

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  1. Low Power SRAMVLSI Final Presentation Stephen Durant Ryan Kruba Matt Restivo Voravit Vorapitat

  2. High Level Architecture ADDR 5:32 Block Enable SRAM Block OUT

  3. Block I/O SRAM Block READ WRITE ADDR OUT DATA BLK ENABLE

  4. Output Buffering SRAM Block BLK_EN0 ADDR 13:12 Sense Amp 2:4 Decoder BLK_EN1 ADDR 14 Out BLK_EN2 BLK_EN3

  5. Block Level Architecture BLK_EN Pulse Gen 1 CLK Precharge Decoder 6:64 SRAM Block ADDR BLK_EN Pulse Gen 1 Pulse Gen 2 Delay SA SA SA SA Write

  6. Input Gating READ Register WRITE ADDR DATA Buffer SRAM Block x8 ADDR 14:13

  7. Word Line Pulse • Pulse WL to reduce the drop in bit line voltage during a read • Size the inverters to create min WL pulse length • min WL pulse occurs before the point where the sense amp can no longer execute a read

  8. Sense Amp Enabling • Sense amp enabled after WL pulse to maximize differential current • Wordline pulse generator clocks a second pulse generator to ensure proper SA timing • SAE signal and precharge signal separate to allow outputs to hold to end of clock cycle

  9. Sense Amp • Size the three nmos transistors to control: • Bit line voltage drop • Delay

  10. Gate Length Vs. Bit Line Voltage DropUsing a 5 V vdd and allowing OutB to drop to 4 V min

  11. Delay from SAE to Out • From 50% SAE high to 50% Out low • Same parameters as bit line voltage graph

  12. Memory Partitioning • 32 blocks *256 rows *128 columns • balance between idle block power savings and peripheral circuitry • resulting block aspect ratio relatively square to limit maximum WL/BL capacitances • WL partitioning and four words/row to reduce power

  13. Multiple voltage sources to accurately measure energy Wordline, active column, inactive column, and peripheral Etotal = EWL+32Eact+96Einact+Eperipheral Simulation Model

  14. Low Power Techniques

  15. Optimal Signal Order for Energy Goal: Making WL pulse as short as possible. Read SAE must be asserted only after WL pulse ends. Write WL pulse must start after BL or BLB completely discharged.

  16. WL Write ’0’ Read Write ’1’ Read CLK BL SAE

  17. Lower Vdd Energy=CeffVdd2 (Rail to Rail) -Expected quadratic energy reduction Energy=CeffVdd∆V (BL/BLB during read) - ∆V should scale down but may not be as fast as Vdd so we expect between linear and quadratic energy reduction.

  18. Simulation Result for 1 bit Note: The Read/Write/Dread shown here is BL energy only

  19. How far should we go?

  20. Clock Gating Try to reduce the capacitance that high activity signal have to drive. Example: WL Pulse which have to drive 256 of 2-input NAND!

  21. Level 1 Level 0 EffLoad=256 EffLoad=128+2

  22. Even Further Level 2 EffLoad=64+4

  23. Simulation Result

  24. Some note about clock gating It act like a decoder, in our design we choose to use level 2 clock gating for WL pulse so we did not need 8 to 256 decode any more, we just need the 6 to 64.

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