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Event Master Driver Design Review

Event Master Driver Design Review. Johnny Tang (BNL) SNS Global Controls. Outline. Event Driver Design Requirements V123S and V101 Board VME Memory Map and Register Bit Assignments Event Master Driver Design Block Diagram Event Master Driver - bsyncDrv Initialization IOCTL Functions

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Event Master Driver Design Review

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  1. Event Master Driver Design Review Johnny Tang (BNL) SNS Global Controls

  2. Outline • Event Driver Design Requirements • V123S and V101 Board VME Memory Map and Register Bit Assignments • Event Master Driver Design Block Diagram • Event Master Driver - bsyncDrv • Initialization • IOCTL Functions • Interrupt Handling • EPICS Interface • EPICS Device Support • Test Application • Event Master Documentations • Summary – Current Status

  3. Event Master Driver Design Requirements • Compatible with SNS ADE • Provide Board Configuration & Status Access Routines • Support V123S and V101 Board Functionalities • Compliant with Wind River Coding Conventions • VxWorks naming conventions (routines, variables, constants, macros, types, structure and error status codes) • Unique status codes assigned for each error • Subroutines must be preceded by a comment block containing the purpose of the subroutine • Parameterize base address, interrupt number & vector

  4. Event Input Board Register VME Memory Map /* Control registers for the input modules. */#define INP_VMEID 0#define INP_CHAN_ENABLE 0x40#define INP_CHAN_INT_ENABLE 0x42#define INP_CHAN_TRIGGER 0x44#define INP_CHAN_ERROR 0x46/* macro for input module register access */#define INP_REG(baseAddress, index, reg) *((unsigned volatile char *) baseAddress + INP_BASE_ADDRESS_OFFSET + index * INP_ADDRESS_SIZE + reg)/* macros for specific registers */#define INP_CHAN_ENABLE_REG_MSB(baseAddress, index) INP_REG(baseAddress, index, INP_CHAN_ENABLE)#define INP_CHAN_ENABLE_REG_LSB(baseAddress, index) INP_REG(baseAddress, index, INP_CHAN_ENABLE+1)#define INP_CHAN_INT_ENABLE_REG_MSB(baseAddress, index) INP_REG(baseAddress, index, INP_CHAN_INT_ENABLE)#define INP_CHAN_INT_ENABLE_REG_LSB(baseAddress, index) INP_REG(baseAddress, index, INP_CHAN_INT_ENABLE+1)#define INP_CHAN_TRIGGER_REG_MSB(baseAddress, index) INP_REG(baseAddress, index, INP_CHAN_TRIGGER)#define INP_CHAN_TRIGGER_REG_LSB(baseAddress, index) INP_REG(baseAddress, index, INP_CHAN_TRIGGER+1)#define INP_CHAN_ERROR_REG_MSB(baseAddress, index) INP_REG(baseAddress, index, INP_CHAN_ERROR)#define INP_CHAN_ERROR_REG_LSB(baseAddress, index) INP_REG(baseAddress, index, INP_CHAN_ERROR+1) /* offset from encoder module base address */#define INP_BASE_ADDRESS_OFFSET 0x800/* offset between input modules */#define INP_ADDRESS_SIZE 0x80

  5. Event Encoder Board Register VME Memory Map /* Control registers for the BSYNC encoder module. */#define ENC_VMEID 0#define ENC_CSR 0x201#define ENC_INT_VEC 0x203#define ENC_INT_LEV 0x205#define ENC_INP_INT_VEC 0x207#define ENC_FIFO 0x209#define ENC_ERR_REG 0x20d #define ENC_RT_STATUS 0x20f #define ENC_EVENT_CODE_TABLE 0x400/* Encoder module event code table size in bytes. */#define ENC_EVENT_CODE_TABLE_SIZE (BSYNC_INPUT_MAX_MODULES * BSYNC_INPUT_NUM_CHANNELS)/* Command and status bits for encoder module CSR register */#define ENC_BCF (1<<7) /* 1 for clock failure */#define ENC_ACS (1<<6) /* 1 for Automatic Clock Switch on */#define ENC_FF (1<<5) /* 1 for FIFO full */#define ENC_KOA (1<<3) /* 1 for release on acknowledge ; 0 for release on reg access */#define ENC_CLK (1<<2) /* 1 for internal clock */#define ENC_INT (1<<1) /* 1 for interrupt enable */#define ENC_GO (1<<0) /* 1 for system enable *//* Status bits for encoder module RT-Status reg */#define ENC_PT (1<<1) /* 1 for system in between Pre-pulse and T-extract */#define ENC_FE (1<<0) /* 1 for FIFO empty */

  6. Event Encoder Board Register VME Memory Map /* macro for encoder module register access */#define ENC_REG(baseAddress, reg) *((unsigned volatile char *) baseAddress + reg)/* macros for specific registers */#define ENC_CSR_REG(baseAddress) ENC_REG(baseAddress, ENC_CSR)#define ENC_INT_VEC_REG(baseAddress) ENC_REG(baseAddress, ENC_INT_VEC)#define ENC_INT_LEV_REG(baseAddress) ENC_REG(baseAddress, ENC_INT_LEV)#define ENC_INP_INT_VEC_REG(baseAddress) ENC_REG(baseAddress, ENC_INP_INT_VEC)#define ENC_FIFO_REG(baseAddress) ENC_REG(baseAddress, ENC_FIFO)#define ENC_STATUS_REG(baseAddress) ENC_REG(baseAddress, ENC_RT_STATUS)

  7. Event Master Driver Design Block Diagram Application Event Master IOC Startup Script EPICS Support Layer ioctl() close() write() open() ioLib iosDrvInstall() iosLib iosDevAddl() bsyncOpen() bsyncClose() bsyncWrite() bsyncIoctl() bsyncDrv() bsyncDevCreate() bsyncDrv Event Link P2 Bus

  8. Event Master Driver – bsyncDrv.c - Initialization • Initialization This driver provides an interface to the V123 beam-synchronous encoder module and the 16-channel V101 beam-synchronous input modules. Most of the routines in this driver are accessible only through the I/O system. bsyncDrv(), however, must be called directly to install the driver and bsyncDevCreate() to initialize and install each device. After installing the driver and creating the devices the following functions are available; open(), close(), write(), ioctl(). These are available through the VxWorks I/O system. #Install driver int bsyncDrv(void); # Create each beam-sync input or encoder device int bsyncDevCreate(deviceName, baseAddress,  moduleIndex, intLevel, intNumber); char *deviceName  # Name of input or encoder device (e.g. /dev/bsyncEncA, /dev/bsyncInputA).  void *baseAddress  # V123S (encoder module) base address.  signed char moduleIndex  # -1 for encoder, 0-3 for input modules  unsigned char intNumber  # Interrupt number, set separately for encoder and input modules.  unsigned char intLevel  # VMEbus interrupt level, set for encoder, used by input modules

  9. Event Master Driver – bsyncDrv.c – IOCTL Function List • IOCTL Function List BSYNC_ENCODER_REV_TICK_STATUSBSYNC_ENCODER_REV_TICK_FAIL_COUNTBSYNC_ENCODER_CLOCK_STATUSBSYNC_ENCODER_CLOCK_FAIL_COUNTBSYNC_ENCODER_EXTERNAL_EVENT_STATUSBSYNC_ENCODER_EXTERNAL_EVENT_FAIL_COUNTBSYNC_ENCODER_SYNC_STATUSBSYNC_ENCODER_SYNC_FAIL_COUNTBSYNC_ENCODER_AUTO_OVERRIDE_CONTROLBSYNC_ENCODER_AUTO_OVERRIDE_STATUSBSYNC_ENCODER_REV_COUNTER_READBSYNC_ENCODER_REV_COUNTER_CLEARBSYNC_ENCODER_REFRESH_STATUS_BITSBSYNC_INPUT_ENABLEBSYNC_INPUT_DISABLEBSYNC_INPUT_IS_ENABLEDBSYNC_INPUT_TRIGGERBSYNC_INPUT_ERROR_COUNTBSYNC_INPUT_GET_EVENT_LISTBSYNC_INPUT_SET_EVENT_LIST

  10. BSYNC_ENCODER_CLOCK_STATUS Description: Return the current state of the external clock. The V123S depends on an  external beam-synchronous clock at about 33.84 Mhz. If the clock signal does  not occur in a timely manner, the status is set to failed. If the clock  is reestablished, the status reverts to OK. Arg Usage: N/A  Return Value: 1 means clock failed, 0 means clock OK BSYNC_ENCODER_CLOCK_FAIL_COUNT Description: The driver accumulates a count of state changes of the  clock status. Each time the clock status changes  from failed to OK, or vice versa, the count increments.  This count can be used for historical analysis. The  count is maintained by the interrupt service routine.  If interrupts are disabled, the count will not be  properly maintained. Arg Usage: N/A Return Value: Count of state changes of clock status Event Master Driver – bsyncDrv.c – IOCTL Functions

  11. BSYNC_EXTERNAL_EVENT_STATUS Description: Returns one if an external event has occurred. An improperly configured  V101 may produce an out of range event code index.  If this happens, the V123S will "latch" that fact, and this  function will return 1. The latch can be cleared via the  BSYNC_ENCODER_REFRESH_STATUS_BITS ioctl function. Arg Usage: N/A  Return Value: 1 means external event has occurred, 0 means external event state cleared BSYNC_ENCODER_EXTERNAL_EVENT_COUNT Description: The driver accumulates a count of state changes of the  external event status. Each time the external event status changes  from failed to OK, or vice versa, the count increments.  This count can be used for historical analysis. The  count is maintained by the interrupt service routine.  If interrupts are disabled, the count will not be  properly maintained. Currently, the V123S does not issue  an interrupt on this state change. Therefore the count is  always 0. Arg Usage: N/A Return Value: Count of state changes of external event status Event Master Driver – bsyncDrv.c – IOCTL Functions

  12. BSYNC_ENCODER_SYNC_STATUS Description: Return the current state of external clock synchronization. The V123 depends on an  external beam-synchronous clock at about 33.84 Mhz. If the clock frequency  is too far out of range, the status is set to failed. If synchronization  is reestablished, the status reverts to OK. Arg Usage: N/A  Return Value: 1 means synchronization has failed, 0 means synchronization is OK BSYNC_ENCODER_SYNC_FAIL_COUNT Description: The driver accumulates a count of state changes of the  synchronization status. Each time the synchronization status changes  from failed to OK, or vice versa, the count increments.  This count can be used for historical analysis. The  count is maintained by the interrupt service routine.  If interrupts are disabled, the count will not be  properly maintained. Arg Usage: N/A Return Value: Count of state changes of synchronization status Event Master Driver – bsyncDrv.c – IOCTL Functions

  13. BSYNC_ENCODER_AUTO_OVERRIDE_CONTROL Description: Sets the clock auto/override mode of the V123S.  In automatic mode, the V123S gives preference to the  external clock, but will switch to an internal clock  if the external clock fails. In override mode, the V123S  only uses the internal clock.  Arg Usage: 0 for override mode, non-zero for automatic mode Return Value: OK BSYNC_ENCODER_AUTO_OVERRIDE_STATUS Description: Returns the V123S clock mode. Arg Usage: N/A Return Value: 0 for override mode, 1 for automatic mode Event Master Driver – bsyncDrv.c – IOCTL Functions

  14. BSYNC_INPUT_ENABLE Description: When an input channel is enabled, signals connected to  that channel will produce event codes. Arg Usage: channel number (0-15) Return Value: OK BSYNC_INPUT_DISABLE Description: When an input channel is disabled, signals connected to  that channel will not produce event codes. Arg Usage: channel number (0-15) Return Value: OK BSYNC_INPUT_IS_ENABLED Description: Return the enable status of a channel. Arg Usage: channel number (0-15) Return Value: 1 if enabled, 0 if not Event Master Driver – bsyncDrv.c – IOCTL Functions

  15. BSYNC_INPUT_TRIGGER Description: Simulate a signal connected to a channel to produce an event code. Arg Usage: channel number (0-15) Return Value: OK BSYNC_INPUT_ERROR_COUNT Description: If the input signal frequency is higher than the polling frequency  of the V123S, then not all signals will produce event codes. A  count of "lost" input signals is maintained by the driver,  and returned by this function. The count is maintained  by the interrupt service routine. If interrupts are disabled,  the count will not be properly maintained. Arg Usage: channel number (0-15) Return Value: OK Event Master Driver – bsyncDrv.c – IOCTL Functions

  16. BSYNC_INPUT_GET_EVENT_LIST Description: Return the event codes associated with each of the 16 channels  which comprise the input module. Arg Usage: pointer to user-provided bsyncEventList data structure Return Value: OK BSYNC_INPUT_SET_EVENT_LIST Description: Assign the event codes associated with each of the 16 channels  which comprise the input module. Arg Usage: pointer to user-provided bsyncEventList data structure Return Value: OK Event Master Driver – bsyncDrv.c – IOCTL Functions

  17. Event Master Driver – bsyncDrv.c – Interrupt Handling The interrupt service routine accumulates input errors from various sources. LOCAL void bsyncInputIntHandler(FAST BSYNC_DEV_HEADER *pBsyncDv) { register char chanErr, ix; /* Read in the channel error register to determine event which was lost. (This also clears the error status). */ DEBUG_PRINT("In Input ISR!\n"); /* the status of the 16 channels is encoded into 2 8-bit registers */ chanErr = INP_CHAN_ERROR_REG_LSB(pBsyncDv->pBsyncBaseAddress, pBsyncDv->moduleIndex); if(chanErr){ for( ix=0; ix<8; ix++ ){ if( chanErr & (1<<ix) ){ pBsyncDv->moduleData.inputModuleData->missedEventCount[ix]++; /* disable interrupts (if needed) for a little while */ disableInputInts(pBsyncDv->pBsyncBaseAddress, pBsyncDv->moduleIndex, ix); wdStart( pBsyncDv->watchdogId, pBsyncDv->delay, (FUNCPTR)bsyncInputWD, (int)pBsyncDv ); } } } chanErr = INP_CHAN_ERROR_REG_MSB(pBsyncDv->pBsyncBaseAddress, pBsyncDv->moduleIndex); if(chanErr){ for( ix=8; ix<BSYNC_INPUT_NUM_CHANNELS; ix++ ){ if( chanErr & (1<<(ix-8)) ){ pBsyncDv->moduleData.inputModuleData->missedEventCount[ix]++; /* disable interrupts (if needed) for a little while */ disableInputInts(pBsyncDv->pBsyncBaseAddress, pBsyncDv->moduleIndex, ix); wdStart( pBsyncDv->watchdogId, pBsyncDv->delay, (FUNCPTR)bsyncInputWD, (int)pBsyncDv ); } } } }

  18. Event Master Driver – bsyncDrv.c – Interrupt Handling The interrupt service routine accumulates input errors from various sources. LOCAL void bsyncEncoderIntHandler(FAST BSYNC_DEV_HEADER *pBsyncDv) { static unsigned char CSR = 0; /* what bits have changed (XOR)? */ register unsigned char diff = CSR ^ ENC_CSR_REG(pBsyncDv->pBsyncBaseAddress); DEBUG_PRINT("In Encoder ISR!\n"); /* adjust counters */ if(diff & ENC_BCF) pBsyncDv->moduleData.encoderModuleData->clockFailCount++; /* disable interrupts (if needed) for a while */ if(diff & (ENC_BCF)){ disableEncoderInts(pBsyncDv->pBsyncBaseAddress); wdStart( pBsyncDv->watchdogId, pBsyncDv->delay, (FUNCPTR)bsyncEncoderWD, (int)pBsyncDv ); } /* set local copy of CSR */ CSR ^= diff; }

  19. Event Master EPICS Interface – Device Support • Device Support # EPICS Device Support for EVENT Input Module device(bi,INST_IO,devBiEventInput,"EventInput") device(bo,INST_IO,devBoEventInput,"EventInput") device(waveform,INST_IO,devWfEventInput,"EventInput") # EPICS Device Support for EVENT Encoder Module device(stringin,INST_IO,devStringinEventEncoder,"EventEncoder") device(bi,INST_IO,devBiEventEncoder,"EventEncoder") device(bo,INST_IO,devBoEventEncoder,"EventEncoder")

  20. Event Master EPICS Interface – Test Application

  21. Event Master EPICS Interface – Test Application

  22. Event System Software Documentations http://www.sns.bnl.gov/epics/timing has the following documents : • Event Encoder and Input Driver Manual • Event Master EPICS Device and Driver Support • V123S User Manual Source Code is available in SNS CVS repository at ORNL

  23. Summary • Event Software Driver is in Beta release and is ready for application test • Integration test with Utility or MPS hardware and software will be conducted when these are available in the near future

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