Important Components, Blocks and Methodologies

1. Important Components, Blocks and Methodologies

2. To remember EXORS Counters and Generalized Counters State Machines (Moore, Mealy, Rabin-Scott) Controllers (FSM for control + Data Path) Iterative Circuits Generalized Register Pipelined Cellular Automata Oracle Data Flow Graph Butterfly Ping-Pong Architecture Trees Sequence Generators (permutations, selections, tree-search strategies) Sequence Detectors Sequence Transformers

3. Useful tool for your creativity! architecture Design problem

4. XORs and XNORs

5. XOR

6. XOR gates A  0 = A A  1 = A’ A  A’ = 1 A + B = A  B  AB AB’ + A’B = AB’  A’B A  B’ = A’  B = (A  B)’

7. Cascading XOR gates

8. Parity Generation

9. 74x280 9-bit odd/even parity generator

10. Tree and Iterative circuits

11. Fig.6.74. XORs in comparators • Always two choices: • Tree • Linear array (iterative)

12. Big OR functions

13. Sequence Detectors

14. Sequence Detector • One-input/one-output sequence detector: produces output value 1 every time sequence 0101 is detected, else 0 • Example: 010101 -> 000101 • State diagram and state table: • Transition and output tables:

15. Sequence Detector (Contd.) Excitation and output maps: Logic diagram: z = xy1y2’ y1 = x’y1y2 + xy1’y2 + xy1y2’ y2 = y1y2’ + x’y1’ + y1’y2 Clock in D type synchronized FF is not shown

16. Sequence Detector (Contd.) Another state assignment: z = xy1y2 Y1 = x’y1y2’ + xy2 Y2 = x’ State assignment is really important for iterative circuits

17. Big Counters

18. Binary Counter One-input/one-output modulo-8 binary counter: produces output value 1 for every eighth input 1 value State diagram and state table: Mealy table • This is different type of graph of counter that we discussed before. • Earlier the graph had no input and changes to new states corresponded to clock • This graph assumes asynchronous FFs. Stays in the same state

19. Binary Counter (Contd.) Transition and output tables: Excitation table for T flip-flops and logic diagram: T1 = x T2 = xy1 T3 = xy1y2 z = xy1y2y3 Realization with asynchronous FFs, no clock

20. Implementing the Counter with asynchronousSR Flip-flops • Transition and output tables: • Excitation table for SR • flip-flops and logic diagram: • Trivially extensible to • modulo-16 counter • S1 = xy1’ • R1 = xy1 • S2 = xy1y2’ • R2 = xy1y2 S3 = xy1y2y3’ • R3 = z = xy1y2y3 Asynchronous FFs, no clock

21. Counter Problems to think about: • Design a counter modulo 2k • Design a counter modulo 12348 • Design a counter in Gray Code. • Design a counter in arbitrary code. • Design a switchable counter in two codes with two capacities • Design a reversible counter that can count up or down

22. Sequential Parity Generators

23. Parity-bit Generator • Serial parity-bit generator: receives coded messages and adds a parity bit to every m-bit message • Assume m = 3 and even parity • State diagram and state table: J1 = y2 K1 = y2’ J2 = y1’ K2 = y1 J3 = xy1’ + xy2 K3 = x + y2’ z = y2’y3

24. Controllers = (FSM+DataPath)

25. Sequential Circuit as a Control Element • Control element: streamlines computation by providing appropriate control signals • Example: digital system that computes the value of (4a + b) modulo 16 • a, b: four-bit binary number • X: register containing four flip-flops • x: number stored in X • Register can be loaded with: either b or a + x • Addition performed by: a four-bit parallel adder • K: modulo-4 binary counter, whose output L equals 1 whenever the count is 3 modulo 4

26. Example (Contd.) • Sequential circuit M: • Input u: initiates computation • Input L: gives the count of K • Outputs: , , , z • When = 1: contents of b transferred to X • When = 1: values of x and a added and transferred back to X • When = 1: count of K increased by 1 • z = 1: whenever final result available in X

27. Example (Contd.) • Sequential circuit M: • K, u, z: initially at 0 • When u = 1: computation starts by setting = 1 • Causes b to be loaded into X • To add a to x: set = 1 and = 1 to keep track of the number of times a has been added to x • After four such additions:z = 1 and the computation is complete • At this point:K = 0 to be ready for the next computation • State diagram:

28. Example (Contd.) State assignment, transition table, maps and logic diagram: = y1’y2 = = y1y2 z = y1y2’ Y1 = y2 Y2 = y1’y2 + uy1’ + L’y2 Sequential circuit

29. Every student has to know (from ECE 271) • Realization of a state table from a state graph • Encoding of a state table • Realization of a state table with D FFs. • Realization of a state table with JK FFs. • Realization of a state table with T FFs. • Realization of a state table with Iterative Circuit • Synchronous versus asynchronous FFs.

30. Arithmetic Circuits

31. Topics • Adder circuits • How to subtract • Why complemented representation works out so well • Overflow

32. Iterative Circuit • Functional blocks per bit

33. Adders • Great example of this type of design • Design 1-bit circuit, then expand • Let’s look at • Half adder – 2-bit adder, no carry in • Inputs are bits to be added • Outputs: result and possible carry • Full adder – includes carry in, really a 3-bit adder

34. Half Adder • S = X  Y • C = XY

35. Full Adder • Three inputs. Third is Cin • Two outputs: sum and carry

36. Two Half Adders (and an OR) From Truth Table at the left we get this

37. Ripple-Carry Adder • Straightforward – connect full adders • Carry-out to carry-in chain • C0 in case this is part of larger chain, or just ‘0’

38. Iterative Circuits

39. Iterative Combinational Circuits • Iterative network: cascade of identical cells • Sequential: counter, shift register • Combinational • Every finite output sequence that can be produced sequentially by an FSM can also be produced spatially (or simultaneously) by a combinational iterative network • Analogy between iterative networks and sequential machines: • Cell inputs/outputs • Input/output carries

40. Iterative combinational Circuits Another notation and names

41. Iterative Comparators

42. Iterative comparator of equality

43. 74x682 8-bit comparator Faster circuit

44. Cell Table • Cell table: analogous to state table • Example: 0101 pattern detector • Assuming the same assignment for states (A: 00, B: 01, C: 11, D: 10): each cell same as the combinational logic of the sequential circuit derived for the 0101 sequence detector earlier

45. Synthesis • Example: synthesize an n-cell iterative network • Each cell has one cell input xi and one cell output zi • zi = 1: if and only if either one or two of the cell inputs x1, x2, …, xi have value 1 • States A, B, C, D: 0, 1, 2, (3 or more) of the cell inputs to preceding cells have value 1 • Cell table Cell Output-carries and cell-output table

46. Iterative comparator of orders and equality Calculated last week Starts from graph Next table from graph Realize circuit combining identical blocks Last block different Transition from combinational to sequential circuit Main tradeoff of digital design – parallel versus serial

47. General Iterative Circuits

48. Structures of generalized iterative circuits

49. Structures

50. Structures • It seems to be a loop here, but there is no loop • You cannot create a loop that would cause creation of a memory. • Circuit can have a loop but no memory.