1 / 15

Detector Interface (DIF) Status

This document summarizes the key outcomes of the CALICE meeting held at DESY in December 2007, focusing on the Detector Interface (DIF) and its associated systems. It covers the design and functionalities of the Off-Detector Receiver (ODR), Link/Data Aggregator (LDA), and various interface electronics for different detector types, including ECAL, DHCAL, and AHCAL. The presentation also discusses the fast data flow mechanisms, power cycling procedures, and collaborative efforts by the DIF Task Force to enhance detector and data acquisition designs. Future prototype developments and VHDL programming are also highlighted.

matthew-russo
Télécharger la présentation

Detector Interface (DIF) Status

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Detector Interface (DIF) Status Mathias Reinecke CALICE meeting – DESY Dec. 2007

  2. DIF environment – DAQ scheme ODR: Off-Detector Receiver LDA: Link/Data Aggregator DIF: Detector (specific) Interface CCC: Clock/Control/Config Aggregator (mostly common for all detectors) VFE Interface Electronics (common + detector specific parts) ECAL, DHCAL or AHCAL (VFE ASICs and detectors) From M. Wing et al. Mathias Reinecke CALICE meeting – DESY Dec. 2007

  3. LDA Data Flow Data Flow includes: - Control and Configuration Path - Event Readout Path - Fast Access (timing related) From M. Kelly et al. Mathias Reinecke CALICE meeting – DESY Dec. 2007

  4. LDA Prototype Design Commercial Spartan3 FPGA Board • Add-on boards for: • ODR-LDA interface (Ethn) • LDA-DIF interface (HDMI) • First prototypes expected • soon (Manchester). From M. Kelly et al. Mathias Reinecke CALICE meeting – DESY Dec. 2007

  5. LDA - DIF protocol ideas DIF Upstream example: -enables fast (8-bit) commands -block transfer for large amounts of data (e.g. configuration data) -acknowledge to LDA (link robustness) From B. Hommels and M. Goodrick et al. Mathias Reinecke CALICE meeting – DESY Dec. 2007

  6. DIF common blocks From B. Hommels and M. Goodrick et al. Mathias Reinecke CALICE meeting – DESY Dec. 2007

  7. DIF working group A „DIF Task Force“ has been established in order to exploit the synergies of the detector- and DAQ designs. • Bart Hommels (Cambridge) for the DAQ - Remy Cornat (Clermont) for the ECAL - Julie Prast (Annecy) for the DHCAL • - Mathias Reinecke (DESY) for the AHCAL • Signal interface DIF – Slab has been defined (ASIC prototypes). • VHDL programming in progress (DIF, test prototypes) • -Website with common VHDL blocks in preparation (J. Prast et al.) • -Current status and upcoming questions => report Mathias Reinecke CALICE meeting – DESY Dec. 2007

  8. DIF – Slab Common Signal List List for ASIC‘s prototypes operation. Additional functionalities (e.g. failsafe) for next version under investigation. Mathias Reinecke CALICE meeting – DESY Dec. 2007

  9. Power Cycling (e.g. SPIROCs) • Sequential power cycling of digital part during readout, • controlled by readout token. • (in this example: SPIROC with 5 analogue stages : • individual channel trigger, • SIPM noise above threshold rate ≈ 300Hz). Mathias Reinecke CALICE meeting – DESY Dec. 2007

  10. DIF – AHCAL specific part Mathias Reinecke CALICE meeting – DESY Dec. 2007

  11. AHCAL Half Sector - Reminder AHCAL Slab 6 HBUs in a row HBU HCAL Base Unit typ. 12 x 12 tiles SPIROC typ. 4 on a HBU HEB HCAL Endcap Board Hosts mezzanine modules: DIF, CALIBand POWER HLD HCAL Layer Distributor Mathias Reinecke CALICE meeting – DESY Dec. 2007

  12. AHCAL: Unit CALIB • Gain calibration, -monitoring and operational tests by controlling the: POWERCALIBDIF • -Charge injection circuits • (SPIROC‘s charge inj. inputs) • Light calibration (LED) system • External trigger (without or in • combination with LCS) • Power cycling for electronics inside • detector layer To LDA Unit CALIB is fully controlled by the DIF (slave operation). Mathias Reinecke CALICE meeting – DESY Dec. 2007

  13. AHCAL: Unit POWER+Monitoring • Power supply for the HBUs, • monitoring of temperature and • supply voltages POWERCALIBDIF • -Provide +3.5V, +5V and SiPM bias • voltages (+GND) to the HBUs • Read temperature monitors from • HBUs (inside gap) • Read voltage/current monitors of • supply voltages (outside gap). • Power cycling for electronics inside • detector layer To LDA Unit POWER is fully controlled by the DIF (slave operation). Mathias Reinecke CALICE meeting – DESY Dec. 2007

  14. DIF: AHCAL specific part Very first idea about a possible setup. Mathias Reinecke CALICE meeting – DESY Dec. 2007

  15. DIF – AHCAL Interconnection HBU Interconnection „Flexlead“ (4 layers in 300µm) POWERCALIBDIF Connector stacking height (both parts): 800µm Mathias Reinecke CALICE meeting – DESY Dec. 2007

More Related