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Sustaining the Exponential Growth of Embedded DSP Capability †

This workshop explores the challenges and implications of sustaining the exponential growth of embedded DSP capability, including historical perspective, IC density growth impediments, and the role of algorithms. Sponsored by the Department of the Air Force.

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Sustaining the Exponential Growth of Embedded DSP Capability †

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  1. Sustaining the Exponential Growth of Embedded DSP Capability† High Performance Embedded Computing Workshop 28 September 2004 Dr. Gary Shaw Dr. Mark Richards MIT Lincoln Laboratory Georgia Institute of Technology †This work was sponsored by the Department of the Air Force under Contract F19628-00-C-0002.Opinions, interpretations, conclusions, and recommendations are those of the author and are not necessarily endorsed by the United States Government. MIT Lincoln Laboratory

  2. Elements Contributing to Embedded Processor Performance

  3. Outline • Historical perspective – fulfillment of Moore’s Law • Impediments to continued IC density growth • Algorithms – the softer side of exponential growth • Implications regarding sustaining exponential growth • Summary and Conclusions

  4. Moore’s Law: Prediction and Realization 2x every ~1.9 years Original Prediction (Source: Electronics 1965) 2x every year Source: Intel John von Neumann: “Truth is much too complicated to allow anything but approximations.” Gordon Moore: “If Al Gore invented the Internet, I invented the exponential”

  5. Top 500 Computer Growth 2x every 1.1 year

  6. Outline • Historical perspective - fulfillment of Moore’s Law • Impediments to continued IC density growth • Heat dissipation • Quantum effects • Production technology • Algorithms – the softer side of exponential growth • Implications regarding sustaining exponential growth • Summary and Conclusions 

  7. Performance Implications of Shrinking Feature Size Energy per Instruction 100000 10000 Frantz 1000 Smailagic Intel trend 100 10 nJ/Instruction 1 -2x every 1.8 years 0.1 0.01 0.001 1965 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 2020 Year D feature size

  8. Moore’s Law Growth in Power Density 1000 nuclear reactor fuel cell 100 Pentium 4 space shuttle tile Pentium II Pentium MMX 10 i486 Pentium hot plate i386 1 1985 1990 1995 2000 2005 2010 2x in 3.3 years Power Density (W/cm2) Year

  9. Moore’s Law is Dead, Long Live Moore’s Law!Theory & Practice: Feature Size for MOSFET Devices It's tough to make predictions, especially about the future. - Yogi Berra Gate Length (mm) Year Sources: Combined graph and original concept: Lance Glasser, former Director, DARPA/ETO Theory: Provided by Prof. David Ferry, Arizona State University Practice:The National Technology Roadmap for Semiconductors (SIA Publication, 1994)

  10. Capitalization Cost Impediments Intel withdraws from DRAM market due to estimated ~ $400M capitalization cost 100 Extrapolation 10 ROI Risk Limited? 2x every 3 years 12” fab $3-4B 1 Wafer-Fab Capital Cost ($B) 0.1 0.01 1990 2000 2010 2020 1970 1980 Year Adapted from:

  11. Fulfillment and Impact of Moore’s Prediction Biological Computing? Funda- mental Limits Scaling Rules Naïve, low-order implementations Paradigm Shift? Process Innovations Design Tool Innovations Quantum Computing? • Silicon CMOS IC fabrication technology • Examples of far-reaching impact Transistors 102 109 Year 1965 2005 2015? Altair 8800, 1975 Itanium, 2005 Loosely-Coupled Hardware & Software Design Methodologies Exponential Improvements In Computing at a Fixed Price Point Embedded Processors For Real-time Digital Signal Processing Low-power Wireless Applications

  12. Outline • Historical perspective - fulfillment of Moore’s Law • Impediments to continued IC density growth • Algorithms – the softer side of exponential growth • Implications regarding sustaining exponential growth • Summary and Conclusions 

  13. Elements Contributing to Embedded Processor Performance Hardware Hardware Software Software Computer IC Devices IC Devices Algorithms Functionality Functionality Architecture Signal Processor Signal Processor Hardware Software Computer Computer IC Devices Algorithms Algorithms Functionality Architecture Architecture

  14. Different Character of Hardware (IC) Vs. Algorithm Improvements

  15. Computational Complexity Reduction Afforded by the FFT Over a Sum-of-Products DFT

  16. Moore’s-Law Equivalent Years Required to Match FFT Computational Speedup Years of Hardware Improvement Required for Equal Computational speedup Radix-2 FFT Length

  17. Exponential Improvement in Modem Rates 100000 10000 1000 100 1984 1986 1988 1990 1992 1994 1996 1998 2000 2x every 1.8 years Downstream Data Rate (bps) Year

  18. Application Maturation Cycle

  19. Pulse-Doppler Radar Example LPF I A/D Matrix Transpose Matrix Transpose Time-Domain Matched Filter BPF cos(wot) RF A/D A/D LPF LO Q sin(wot) Doppler DFT Doppler FFT LPF LPF Range FFT RF I + jQ Chirp j n • Algorithmically naïve implementation • Reduced-order implementation with digital I/Q

  20. Pulse-Doppler Radar Algorithm Improvements Radix-2 FFT Radix-4 FFT Goertzel Fast Convolution GOPS Digital I/Q Stretch Processing Moore’s Law Reference slope Year

  21. Outline • Historical perspective - fulfillment of Moore’s Law • Impediments to continued IC density growth • Algorithms – the softer side of exponential growth • Implications regarding sustaining exponential growth • Summary and Conclusions 

  22. IC Vs. Algorithm Development (A Contrived but Useful Analogy) Biological Computing? Silicon lithographic fabrication technology Funda- mental Limits Funda- mental Limits Order Reductions Scaling Rules Naïve, high-order implementations Naïve, low-order implementations Paradigm Shift? Architecture Innovations Process Innovations Design Tool Innovations Quantum Computing? H/W & S/W Codesign Tools Nonlinear Algorithms? • Algorithms Paradigm Shift? Linear algebraic representations and processing Quantum Signal Processing? • ICs

  23. Increased Emphasis on Codesign Methodologies

  24. Wafer-Fab Capitalization Cost Compared to Annual DSP Algorithm R&D Costs Capital cost for state-of-the-art wafer fab facility Annual R&D support for entire IEEE SP Society membership (18,500 x $150K in 2001) 1.11x every 3 years† 1990 2000 2010 2020 1970 1980 †Salary inflation rate based on US Bureau of Labor and Statistics Median Engineering Salaries 1983-2003 100 10 $B 1 2x every 3 years 0.1 0.01 Year

  25. Summary and Conclusions • Fulfilling Moore’s Law • Enabled by diverse, innovative R&D aimed at realizing a common vision (ITRS semiconductor roadmap) • Continued improvements may be impeded by a combination of thermal, quantum, and capital cost limits • Taking up the slack • Over same 40-year time frame as Moore’s Law, algorithm innovation has yielded exponentially improving performance as well • Algorithm innovation also enabled by diverse R&D, but without as clear of an industry-wide common vision • Algorithm R&D cost growth significantly lower than fab capital cost growth (1.1x vs. 2x every 3 years) • Increasing the effectiveness of algorithm R&D • Develop better methods for quantifying the return on investment for algorithm R&D • Consider mechanisms for developing a broader industry vision and commitment to a long-term R&D roadmap • Hardware/software codesign methods increasingly important

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