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Enhancing DPI+ Standards for Multi-Threaded C/C++ and HDL Environments

This proposal outlines enhancements to the DPI+ standards to address existing requirements and emerging needs for system-on-chip (SoC) design. Key focuses include performance in emulated environments, support for multi-threaded C/C++ frameworks, and alignment with other modeling standards. Emphasizing ease of use, model reusability, and determinism, the enhancements aim to facilitate streamlined integration and synchronization while ensuring the capability for multi-lingual HDL support (Verilog, VHDL). The proposals advocate for better mapping to accelerator platforms and retaining determinism even with streaming support.

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Enhancing DPI+ Standards for Multi-Threaded C/C++ and HDL Environments

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  1. DPI+ Proposals John Stickley, Duaine Pryor Mentor Emulation Division

  2. Existing Requirements • Long standing requirements for SCE-MI I • Performance in emulated environments • Transaction oriented • Support for multi-threaded C/C++/HVL TB modeling environments • Multi-lingual on HDL side (Verilog, VHDL) • Previously discussed requirements for SCE-MI II (fall 2003): • No more uncontrolled time • Variable length messages DPI+ Proposals

  3. New Requirements ? • Fusion, alignment with other standards efforts • Emphasis on ease of use for the user and the model writer • Model reusability • Determinism (a.k.a. repeatability) • Streaming support (while retaining determinism) • Synchronization to (not just “support for”) multi-threaded C++ environments • Easy mapping to accelerator platforms (synthesizeability) DPI+ Proposals

  4. Messages (big vectors) Signals Parametrized TLM FIFOs Function Calls + Arguments Existing Standards – Abstraction Space“Sweet Spots” HVL/C/C++Abstraction HDL Abstraction Conduits What is TLM here ?Is it behavioral ?(Is it synthesizeable ?) Behavioral HDL, “RTL+” CC* HDL(can be synthesizeable) RTL CC* HDL(synthesizeable) Behavioral HDL,RTL CC* HDL(partly synthesizeable),Timed gate level *TLM WG term for “cycle callable” meaning “cycle accurate” DPI+ Proposals

  5. Proposal for DPI+ • Is there some “common ground” for existing transaction based modeling standards ? • Can parts be combined where they are serving the same conceptual purpose ? • Can the combined standard still meet past and current requirements ? • Can the combined standard leverage existing, implemented, proven standards without re-inventing the wheel ? DPI+ Proposals

  6. Signals Parametrized TLM FIFOs Function Calls + Arguments Proposed Standards – Abstraction Space“Sweet Spots” HVL/C/C++Abstraction HDL Abstraction Conduits What is TLM here ?Is it behavioral ?(Is it synthesizeable ?) Behavioral HDL,“RTL+” CC* HDL(can be synthesizeable) Behavioral HDL,RTL CC* HDL(partly synthesizeable),Timed gate level *TLM WG term for “cycle callable” meaning “cycle accurate” DPI+ Proposals

  7. DPI+ Proposals

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