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Encoders/Decoders

Encoders/Decoders. Overview. Design Procedure Code Converters Binary Decoders Expansion Circuit implementation Binary Encoders Priority Encoders. Combinational Circuit Design. Design of a combinational circuit is the development of a circuit from a description of its function.

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Encoders/Decoders

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  1. Encoders/Decoders

  2. Overview • Design Procedure • Code Converters • Binary Decoders • Expansion • Circuit implementation • Binary Encoders • Priority Encoders Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  3. Combinational Circuit Design • Design of a combinational circuit is the development of a circuit from a description of its function. • Starts with a problem specification and produces a logic diagram or set of boolean equations that represent the circuit. Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  4. Design Procedure • Determine the required number of inputs and outputs and assign variables to them. • Derive the truth table that defines the required relationship between inputs and outputs. • Obtain and simplify the Boolean function (K-maps, algebraic manipulation, CAD tools, …). Consider any design constraints (area, delay, power, available libraries, etc). • Draw the logic diagram. • Verify the correctness of the design. Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  5. Design Example • Design a combinational circuit with 4 inputs that generates a 1 when the # of 1s equals the # of 0s. Use only 2-input NOR gates … Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  6. More Examples - Code Converters • Code Converters transform/convert information from one code to another: • BCD-to-Excess-3 Code Converter • Useful in some cases for digital arithmetic • BCD-to-Seven-Segment Converter • Used to display numeric info on 7 segment displays

  7. BCD-to-Excess-3 Code Converter • Design a circuit that converts a binary-coded-decimal (BCD) codeword to its corresponding excess-3 codeword. • Excess-3 code: Given a decimal digit n, its corresponding excess-3 codeword (n+3)2Example: n=5  n+3=8  1000excess-3n=0  n+3=3  0011excess-3 • We need 4 input variables (A,B,C,D) and 4 output functions W(A,B,C,D), X(A,B,C,D), Y(A,B,C,D), and Z(A,B,C,D). Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  8. BCD-to-Excess-3 Converter (cont.) • The truth table relating the input and output variables is shown below. • Note that the outputs for inputs 1010 through 1111 are don't cares (not shown here). Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  9. Maps for BCD-to-Excess-3 Code Converter The K-maps for are constructed using the don't care terms Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  10. BCD-to-Excess-3 Converter (cont.) Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  11. a f b g e c Another Code Converter Example:BCD-to-Seven-Segment Converter • Seven-segment display: • 7 LEDs (light emitting diodes), each one controlled by an input • 1 means “on”, 0 means “off” • Display digit “3”? • Set a, b, c, d, g to 1 • Set e, f to 0 d Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  12. BCD-to-Seven-Segment Converter • Input is a 4-bit BCD code  4 inputs (w, x, y, z). • Output is a 7-bit code (a,b,c,d,e,f,g) that allows for the decimal equivalent to be displayed. • Example: • Input: 0000BCD • Output: 1111110 (a=b=c=d=e=f=1, g=0) a f b g e c d Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  13. BCD-to-Seven-Segment (cont.)Truth Table ?? Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  14. Decoders • A combinational circuit that converts binary information from n coded inputs to a maximum 2n decoded outputs  n-to- 2ndecoder • n-to-m decoder, m ≤ 2n • Examples: BCD-to-7-segment decoder, where n=4 and m=7 Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  15. Decoders (cont.) Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  16. 2-to-4 Decoder Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  17. 2-to-4 Active Low Decoder Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  18. 3-to-8 Decoder address data Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  19. 3-to-8 Decoder (cont.) • Three inputs, A0, A1, A2, are decoded into eight outputs, D0 through D7 • Each output Di represents one of the minterms of the 3 input variables. • Di = 1 when the binary number A2A1A0 = i • Shorthand: Di = mi • The output variables are mutually exclusive; exactly one output has the value 1 at any time, and the other seven are 0. Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  20. Implementing Boolean functions using decoders • Any combinational circuit can be constructed using decoders and OR gates! Why? • Here is an example:Implement a full adder circuit with a decoder and two OR gates. • Recall full adder equations, and let X, Y, and Z be the inputs: • S(X,Y,Z) = X+Y+Z = m(1,2,4,7) • C(X,Y,Z) = m(3, 5, 6, 7). • Since there are 3 inputs and a total of 8 minterms, we need a 3-to-8 decoder. Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  21. Implementing a Binary Adder Using a Decoder S(X,Y,Z) = Σm(1,2,4,7) C(X,Y,Z) = Σm(3,5,6,7) Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  22. Decoder Expansions Larger decoders can be constructed using a number of smaller ones. -> HIERARCHICAL design! Example:A 6-to-64 decoder can be designed using four 4-to-16 and one 2-to-4 decoders. How? (Hint: Use the 2-to-4 decoder to generate the enable signals to the four 4-to-16 decoders). Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  23. 3-to-8 decoder using two 2-to-4 decoders Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  24. 4-input tree decoder Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  25. Encoders • An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2n input lines and n output lines. • The output lines generate the binary equivalent of the input line whose value is 1. Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  26. Encoders (cont.) Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  27. Encoder Example • Example: 8-to-3 binary encoder (octal-to-binary) A0 = D1 + D3 + D5 + D7 A1 = D2 + D3 + D6 + D7 A2 = D4 + D5 + D6 + D7 Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  28. Encoder Example (cont.) Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  29. Simple Encoder Design Issues • There are two ambiguities associated with the design of a simple encoder: • Only one input can be active at any given time. If two inputs are active simultaneously, the output produces an undefined combination (for example, if D3 and D6 are 1 simultaneously, the output of the encoder will be 111. • An output with all 0's can be generated when all the inputs are 0's,or when D0 is equal to 1. Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  30. Priority Encoders • Solves the ambiguities mentioned above. • Multiple asserted inputs are allowed; one has priority over all others. • Separate indication of no asserted inputs. Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  31. Example: 4-to-2 Priority EncoderTruth Table Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  32. 4-to-2 Priority Encoder (cont.) • The operation of the priority encoder is such that: • If two or more inputs are equal to 1 at the same time, the input in the highest-numbered position will take precedence. • A valid output indicator, designated by V, is set to 1 only when one or more inputs are equal to 1. V = D3 + D2 + D1 + D0 by inspection. Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  33. Example: 4-to-2 Priority EncoderK-Maps Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  34. Example: 4-to-2 Priority EncoderLogic Diagram Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  35. 8-to-3 Priority Encoder Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  36. A Matrix of switches = Keypad C0 C1 C2 C3 1 2 3 F R0 4 5 6 E R1 7 8 9 D R2 0 A B C R3 Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  37. Keypad Decoder IC - Encoder COL. 4-bit 4-bit Binary (encoded) 1 2 3 F 4 5 6 E ROW 4-bit 7 8 9 D 0 A B C Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  38. Priority Interrupt Encoder Schematic Interrupting Devices Interrupt Encoder Microprocessor Device A Req(1:0) Device B Device C Device D IntRq Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

  39. Priority Encoding - Interrupt Requests Exercise: Complete this table? Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)

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