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Multiplexers Decoders Encoders Code converters Arithmetic comparison circuits PowerPoint Presentation
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Multiplexers Decoders Encoders Code converters Arithmetic comparison circuits

Multiplexers Decoders Encoders Code converters Arithmetic comparison circuits

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Multiplexers Decoders Encoders Code converters Arithmetic comparison circuits

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  1. Multiplexers • Decoders • Encoders • Code converters • Arithmetic comparison circuits • VHDL for combinational circuits

  2. Multiplexers s f s w w 0 0 0 0 f w 1 w 1 1 1 (b) Truth table (a) Graphical symbol w w 0 0 s s f w w f 1 1 (d) Circuit with transmission gates (c) Sum-of-products circuit Figure 6.1 A 2-to-1 multiplexer

  3. s 0 s s s f 1 1 0 w w 00 0 0 0 0 w 01 w 1 0 1 f 1 w 10 w 2 1 0 2 w 11 3 w 1 1 3 (a) Graphic symbol (b) Truth table s 0 w 0 s 1 w 1 f w 2 w 3 (c) Circuit Figure 6.2 A 4-to-1 multiplexer

  4. s 1 s 0 w 0 0 w 1 1 0 f 1 w 0 2 w 1 3 Figure 6.3 Using 2-to-1 multiplexers to build a 4-to-1 multiplexer

  5. s 0 s 1 w 0 w 3 s w 2 4 s 3 w 7 f w 8 w 11 w 12 w 15 Figure 6.4 A 16-to-1 multiplexer

  6. s x y 1 1 x y 2 2 (a) A 2x2 crossbar switch x 0 1 y 1 1 s x 0 2 y 2 1 (b) Implementation using multiplexers Figure 6.5 A practical application of multiplexers

  7. Figure 6.6 Implementing programmable switches in an FPGA

  8. Synthesis of a logic function using multiplexers w w w f 2 1 2 w 1 0 0 0 0 1 0 1 1 f 1 1 0 1 0 0 1 1 (a) Implementation using a 4-to-1 multiplexer w w f 1 2 f w 1 w 1 0 0 0 w 0 2 1 0 1 w w 1 2 2 1 1 0 f 0 1 1 (c) Circuit (b) Modified truth table Figure 6.7 Synthesis of a logic function usingmultiplexers

  9. w w w f 1 2 3 w w f 1 2 0 0 0 0 0 0 0 0 0 1 0 w 0 1 3 0 1 0 0 w 1 0 3 0 1 1 1 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 (a) Modified truth table w 2 w 1 0 w 3 f 1 (b) Circuit Figure 6.8 Three-input majority function

  10. w w w f 1 2 3 0 0 0 0 0 0 1 1 w Å w w 2 2 3 w 0 1 0 1 1 w 0 1 1 0 3 1 0 0 1 f 1 0 1 0 Å w w 2 3 1 1 0 0 1 1 1 1 (a) Truth table (b) Circuit Figure 6.9 Three-input XOR function

  11. w w w f 1 2 3 0 0 0 0 w 3 w 0 0 1 1 2 w 1 0 1 0 1 w 3 w 0 1 1 0 3 1 0 0 1 f w 3 1 0 1 0 1 1 0 0 w 3 1 1 1 1 (b) Circuit (a) Truth table Figure 6.10 Three-input XOR function

  12. w w w f 1 2 3 f 0 0 0 0 w 1 0 0 1 0 w w 0 2 3 0 1 0 0 w + w 1 2 3 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 (b) Truth table w 1 w 2 w 3 f (b) Circuit Figure 6.11 Three-input majority function using a 2-to-1 MUX

  13. Boole’s (Shannon’s) Expansion f(w1,w2,...,wn) = w1 f(0,w2,...,wn) + w1 f(1,w2,...,wn) = w1fw1 + w1fw1 = w1 w2  f(0,0,w3,...,wn) + w1 w2 f(0,1,w3,...,wn) + w1 w2 f(1,0,w3,...,wn) + w1 w2 f(1,1,w3,...,wn)

  14. f = w1w2 + w1w3 + w2w3 Shannon’s F=W1’(W2W3)+W1(W2+W3) F=w2’(w1w3)+w2(w1+w3)

  15. f = w1’w3 + w2w3’ Decomposition using w1 gives F=W1’(W3+W2W3’)+W1(W2W3’) F=W1’(W3+W2)+W1(W2W3’) Decomposition using w2 gives Decomposition using w3 gives

  16. f = w1’w3‘+ w1w2 +w1w3 F=w1’(w3’)+w1(w2+w3) F=w1’w2’(w3’)+w1’w2(w3’) +w1w2’(w3)+w1w2(1) Figure 6.12 Example circuits

  17. w w 2 1 0 w 3 f 1 f = w1w2 + w1w3 + w2w3 g=w2’(0)+w2(w3) h=w2’(w3)+w2(1) Figure 6.13 Example circuit

  18. f = w2’w3+w1’w2w3’+ w2w3’w4+w1w2’w4’ F=w1’fw1’+w1fw1 =w1’(w2’w3+w2w3’+w2w3’w4) +w1(w2’w3+w2w3’w4+w2’w4’) F=w2’fw2’+w2fw2 =w2’(w3+w1w4’)+w2(w1’w3’+w3’w4)

  19. w 1 0 f w 1 w f 2 w 3 f w 1 w 4 (a) Using three 3-LUTs w 2 0 w f f 1 w 2 w 3 w 4 (b) Using two 3-LUTs Figure 6.14 Example circuits

  20. 2. DECODERS w y 0 0 n n 2 inputs w outputs n – 1 y n Enable 2 – 1 En Figure 6.15 An n-to-2n decoder

  21. w w y y y y En 1 0 0 1 2 3 w y 0 0 0 0 0 1 0 0 1 w y 1 1 0 1 0 1 0 0 1 y 2 1 1 0 0 0 1 0 y En 3 1 1 1 0 0 0 1 x x 0 0 0 0 0 (a) Truth table (b) Graphic symbol w 0 y 0 w 1 y 1 y 2 y 3 En (c) Logic circuit Figure 6.16 A 2-to-4 decoder

  22. w y w y 0 0 0 0 w y w y 1 1 1 1 y y 2 2 w y 2 y En 3 3 y w y En 4 0 0 y w y 5 1 1 y y 6 2 y y En 7 3 Figure 6.17 A 3-to-8 decoder using two 2-to-4 decoder

  23. w y w y 0 0 0 0 w y w y 1 1 1 1 y y 2 2 y y En 3 3 y w y 4 0 0 w y y 5 1 1 y y 2 6 w w y y y 2 En 0 0 3 7 w w y 3 1 1 y 2 y w y y En En 8 0 0 3 y w y 9 1 1 y y 2 10 y y En 3 11 y w y 12 0 0 y w y 13 1 1 y y 2 14 y y En 3 15 Figure 6.18 A 4-to-16 decoder built using a decoder tree

  24. w 0 w 1 s w y 0 0 0 s w y f 1 1 1 y w 2 2 y En 1 3 w 3 Figure 6.19 A 4-to-1 multiplexer built using a decoder

  25. w 0 s w y w 0 0 0 1 s w y 1 1 1 f y 2 y En 1 3 w 2 w 3 Figure 6.20 A 4-to-1 multiplexer built using a decoder and tri-state buffers

  26. w 0 y 0 w 1 y 1 y 2 y 3 En Demultiplexers • A demultiplexer is a circuit which places the value of a single data input onto multiple data outputs is a demultiplexer.

  27. Sel 0 0/1 0/1 0/1 Sel 1 0/1 0/1 0/1 Sel a 2 0 0/1 0/1 0/1 decoder a 1 Address m -to-2 a m – 1 m Sel m 2 – 1 0/1 0/1 0/1 Read d d d Data n – 1 n – 2 0 Figure 6.21 A 2m x n read-only memory (ROM) block

  28. 3.ENCODERS w 0 y 0 n n 2 outputs inputs y n – 1 w n 2 – 1 Figure 6.22 A 2n-to-n binary encoder

  29. BINARY ENCODER w w w w y y 3 2 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 1 0 (a) Truth table w 0 w 1 y 0 w 2 y 1 w 3 (b) Circuit Figure 6.23 A 4-to-2 binary encoder

  30. PRIORITY ENCODER w w w w y y z 3 2 1 0 1 0 0 0 0 0 d d 0 0 0 0 1 0 0 1 x 0 0 1 0 1 1 x x 0 1 1 0 1 x x x 1 1 1 1 Figure 6.24. Truth table for a 4-to-2 priority encoder.

  31. 4 CODE CONVERTERS a a f b b w 0 c g w 1 e c d w 2 e c e g w w w w a b d f w d 3 2 1 0 3 f g 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 0 1 1 0 0 0 0 (b) 7-segment display 0 0 1 0 1 1 0 1 1 0 1 (a) Code converter 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 1 1 1 1 1 0 1 1 (c) Truth table Figure 6.25. A BCD-to-7-segment display code converter.

  32. 5 ARITHMETIC COMPARISIONS Figure 6.26. A four-bit comparator circuit.

  33. Libraries • Library ieee; • Use ieee.std_logic_1164.all; • Use ieee.std_logic_arith.all; • Use ieee.std_logic_signed.all; • Use ieee.std_logic_unsigned.all;

  34. Data Types • bit values: '0', '1' • boolean values: TRUE, FALSE • integer values: -(231) to +(231 - 1) • std_logic values: 'U','X','1','0','Z','W','H','L','-' U' = uninitialized 'X' = unknown 'W' = weak 'X‘ 'Z' = floating 'H'/'L' = weak '1'/'0‘ '-' = don't care • Std_logic_vector (n downto 0); • Std_logic_vector (0 upto n);

  35. Entity • Define inputs and outputs • Example: Entity test is Port( A,B,C,D: in std_logic; E: out std_logic); End test;

  36. Architecture • Define functionality of the chip • X <= A AND B; • Y <= C AND D; • E <= X OR Y;

  37. VHDL features • Case insensitive • inputa, INPUTA and InputA are refer to same variable • Comments • ‘--’ until end of line • If you want to comment multiple lines, ‘--’ need to be put at the beginning of every single line • Statements are terminated by ‘;’ • Signal assignment: • ‘<=’ • User defined names: • letters, numbers, underscores (‘_’) • start with a letter

  38. VHDL structure • Library • Definitions, constants • Entity • Interface • Architecture • Implementation, function

  39. VHDL - Library • Include library library IEEE; • Define the library package used use IEEE.STD_LOGIC_1164.all; • Define the library file used • For example, STD_LOGIC_1164 defines ‘1’ as logic high and ‘0’ as logic low • output <= ‘1’; --Assign logic high to output

  40. ABSACCESSAFTERALIASALLANDARCHITECTUREARRAYASSERTATTRIBUTE BEGINBLOCKBODYBUFFERBUS CASECOMPONENTCONFIGURATION CONSTANT DISCONNECTDOWNTO ELSEELSIFENDENTITYEXIT FILEFORFUNCTION GENERATEGENERICGROUPGUARDED IFIMPURE ININERTIALINOUTIS LABELLIBRARYLINKAGELITERALLOOP MAPMOD NANDNEWNEXTNORNOTNULL OFONOPENOROTHERSOUT PACKAGEPORTPOSTPONEDPROCEDUREPROCESSPURE RANGERECORDREGISTERREMREPORTROLROR RETURN SELECTSEVERITYSIGNALSHAREDSLASLLSRASRLSUBTYPE THENTOTRANSPORTTYPE UNAFFECTEDUNITSUNTILUSE VARIABLE WAITWHENWHILEWITH XNORXOR Reserved VHDL keywords

  41. ENTITYnand_gateIS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC ); ENDnand_gate; Entity Declaration • EntityDeclaration describes the interface of the component, i.e. input and output ports. Entity name Port type Port names Semicolon No Semicolon Reserved words Port modes (data flow directions)

  42. Entity declaration – simplified syntax ENTITY entity_name IS PORT ( port_name : signal_mode signal_type; port_name : signal_mode signal_type; …………. port_name : signal_mode signal_type); END entity_name;

  43. Architecture • Describes an implementation of a design entity. • Architecture example: ARCHITECTUREmodelOFnand_gateIS BEGIN z <= aNANDb; ENDmodel;

  44. Architecture – simplified syntax ARCHITECTURE architecture_name OF entity_name IS [ declarations ] BEGIN code END architecture_name;

  45. Entity Declaration & Architecture nand_gate.vhd LIBRARY ieee; USEieee.std_logic_1164.all; ENTITYnand_gateIS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); ENDnand_gate; ARCHITECTUREmodelOFnand_gateIS BEGIN z <= aNANDb; ENDmodel;

  46. Port Modes The Port Mode of the interface describes the direction in which data travels with respect to the component • In: Data comes in this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment. • Out: The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment. • Inout: The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment. • Buffer: Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement the signal can appear on the left and right sides of the <= operator

  47. Library declarations Library declaration Use all definitions from the package std_logic_1164 LIBRARY ieee; USEieee.std_logic_1164.all; ENTITYnand_gateIS PORT( a : IN STD_LOGIC; b : IN STD_LOGIC; z : OUT STD_LOGIC); ENDnand_gate; ARCHITECTUREmodelOFnand_gateIS BEGIN z <= aNANDb; ENDmodel;

  48. Library declarations - syntax LIBRARY library_name; USE library_name.package_name.package_parts;

  49. Fundamental parts of a library LIBRARY PACKAGE 1 PACKAGE 2 TYPES CONSTANTS FUNCTIONS PROCEDURES COMPONENTS TYPES CONSTANTS FUNCTIONS PROCEDURES COMPONENTS

  50. Libraries Need to be explicitly declared Specifies multi-level logic system, including STD_LOGIC, and STD_LOGIC_VECTOR data types • ieee • std • work Specifies pre-defined data types (BIT, BOOLEAN, INTEGER, REAL, SIGNED, UNSIGNED, etc.), arithmetic operations, basic type conversion functions, basic text i/o functions, etc. Visible by default Current designs after compilation