Characteristics of fabrication processes, pixel designs and simulations

1. Characteristics of fabrication processes, pixel designs and simulations A. Dorokhov 09/05/2017

2. substrate/EPI Monolithic active pixel sensors substrate or/and epitaxial layer (p-type) charge collecting electrode (s) (nwell) particle chip is fabricated in CMOS technology: readout electronics fabricated next to charge collecting electrode at the same substrate -> choice of proper fabrication process is important

3. Fabrication of MAPS in CMOS process Twin/Double well process: one can use simple circuitry in pixel-> only NMOS transistors are allowed Low resistive substrate/epitaxial layer (<10 Ohm cm): not easy (or not possible) to deplete detector volume High resistive substrate/epitaxial layer (~>1 kOhm cm), easier to deplete detector volume Triple/quadruple well process -> can use advantage of NMOS and PMOS in the pixel volume first MAPS detector for particle experiment (STAR at RICH), EUDET : AMS technology MAPS development : AMSxx, XFABxx technology ALICE tracker upgrade, CBM tracker: TOWER technology In order to help understanding of operation, get new ideas, verify the performances of the MAPS detector simulation of the sensing elements and readout circuit is needed: device simulation with TCAD and Spectre simulation (Cadence)

4. layout geometry of one pixel MIMOSIS0 chip, transistors are inside Pwell TCAD device simulation of pixel 18um EPI of 10 Ohm cm (low resistivity) Pwell Bias=1V Bias=40V well exclusion area Nwell due to symmetrysimulate only one quarter of rectangular pixel Depletion zone comparable, at 1 V and 40V of bias for different substrates Bias=20V Bias=1V Bias=40V TOWER 18um EPI depletion

5. Bias=40V Bias=20V Bias=1V TCAD device simulation different EPI TOWER 18um EPI TOWER 25um EPI TOWER 30um EPI

6. Results of TCAD device simulation

7. Results of TCAD device simulation

8. Results of TCAD device simulation

9. Results of TCAD device simulation

10. Conclusions for presented example of comparison high resistive substrate and low resistive High resistive substrate: Low resistive substrate: • Helps a lot to deplete pixel volume • Leakage current is larger • Almost no depletion • Leakage current is smaller 3 .capacitance almost not changed 4 . going from pixel pitch 26.88x30.24 to 22x22 does not change much leakage, capacitance and depletion volume, because we do not have full depletion, only the depletion fraction is much larger (x ~2)

11. 40um of 600 Ohm cm Si, 22x22um^2 pitch TCAD device simulation of different pixel geometry surface of Nwells and Pwell exclusions are independent on shape (circular, octagonal or square) circular Nwell, square PWell exclusion circular Nwell, circular PWell exclusion octagonal Nwell, square PWell exclusion octagonal Nwell, circular PWell exclusion

12. Results of TCAD device simulation

13. Results of TCAD device simulation

14. Results of TCAD device simulation

15. Results of TCAD device simulation

16. Conclusions for presented example of comparison different Nwell and Pwell exclusion shapes • The shape of charge collecting diode has marginal influence<few % • The shape of Pwell exclusion has small influence (<10%)