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This document discusses various combinational multiplier architectures, including array and Baugh-Wooley multipliers, focusing on efficiency and layout designs. Key techniques such as pipeline integration and the elimination of registers to enhance performance are explored. Additionally, the paper presents Verilog implementations of array multipliers and discusses the structure of Booth multipliers for two's complement operations. The document aims to provide insights into optimizing multiplication processes in digital circuits through advanced architectural designs.
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Elementary school algorithm 0 1 1 0 multiplicand x 1 0 0 1 multiplier 0 1 1 0 + 0 0 0 0 0 0 1 1 0 + 0 0 0 0 0 0 0 1 1 0 + 0 1 1 0 0 1 1 0 1 1 0 partial product
Word serial multiplier + register
Combinational multiplier Uses n-1 adders, eliminates registers:
Array multiplier • An efficient layout • of a combinational multiplier • May be pipelined • to decrease clock period at the expense of latency.
Array multiplier organization 0 1 1 0 x 1 0 0 1 0 1 1 0 + 0 0 0 0 0 0 1 1 0 + 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 multiplicand multiplier skew array for rectangular layout product
Unsigned array multiplier x2y0 x1y0 x0y0 0 0 x1y1 x0y1 + + x1y2 x0y2 + + xn-1yn-1 0 + + P(2n-1) P0 P(2n-2)
Verilog for multiplier row module multrow(part,x,ym,yo,cin,s,cout); /* A row of one-bit multiplies */ input [2:0] part; input [3:0] x; input ym, yo; input [2:0] cin; output [2:0] s; output [2:0] cout; assign {cout[0],s[0]} = part[1] + (x[0] & ym) + cin[0]; assign {cout[1],s[1]} = part[2] + (x[1] & ym) + cin[1]; assign {cout[2],s[2]} = (x[3] & yo) + (x[2] & ym) + cin[2]; endmodule
Verilog for last multiplier row module lastrow(part,cin,s,cout); /* Last row of adders with full carry chain. */ input [2:0] part; input [2:0] cin; output [2:0] s; output cout; wire [1:0] carry; assign {carry[0],s[0]} = part[0] + cin[0]; assign {carry[1],s[1]} = part[1] + cin[1] + carry[0]; assign {cout,s[2]} = part[2] + cin[2] + carry[1]; endmodule
Verilog for multiplier module array_mult(x,y,p); input [3:0] x; input [3:0] y; output [7:0] p; wire [2:0] row0, row1, row2, row3, c0, c1, c2, c3; /* generate first row of products */ assign row0[2] = x[2] & y[0]; assign row0[1] = x[1] & y[0]; assign row0[0] = x[0] & y[0]; assign p[0] = row0[0]; assign c0 = 3’b000; multrow p0(row0,x,y[1],y[0],c0,row1,c1); assign p[1] = row1[0]; multrow p1(row1,x,y[2],y[1],c1,row2,c2); assign p[2] = row2[0]; multrow p2(row2,x,y[3],y[2],c2,row3,c3); assign p[3] = row3[0]; lastrow l({x[3] & y[3],row3[2:1]},c3,p[6:4],p[7]); endmodule
Baugh-Wooley multiplier • For two’s-complement multiplication. • Adjusts partial products • to maximize regularity of multiplication array. • Moves partial products with negative signs to the last steps • also adds negation of partial products rather than subtracts.
Booth multiplier • Encoding scheme • To reduce number of stages in multiplication. • Performs two bits of multiplication at once • Requires half the stages. • Each stage is slightly more complex than simple multiplier • but adder/subtracter is almost as small/fast as adder.
Serial-parallel multiplier • Used in serial-arithmetic operations. • Multiplicand can be held in place by register. • Multiplier is shfited into array.
