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The Microarchitecture Level

The Microarchitecture Level. Chapter 4. The Data Path (1). The data path of the example microarchitecture used in this chapter. The Data Path (2). Useful combinations of ALU signals and the function performed. Data Path Timing. Timing diagram of one data path cycle. Memory Operation.

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The Microarchitecture Level

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  1. The Microarchitecture Level Chapter 4 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  2. The Data Path (1) The data path of the example microarchitecture used in this chapter. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  3. The Data Path (2) Useful combinations of ALU signals and the function performed. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  4. Data Path Timing Timing diagram of one data path cycle. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  5. Memory Operation Mapping of the bits in MAR to the address bus. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  6. Microinstructions The microinstruction format for the Mic-1. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  7. Microinstruction Control: The Mic-1 (1) The complete block diagram of our example microarchitecture, the Mic-1. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  8. Microinstruction Control: The Mic-1 (2) A microinstruction with JAMZ set to 1 has two potential successors. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  9. Stacks (1) Use of a stack for storing local variables. • While A is active. b) After A calls B. • (c) After B calls C. d) After C and B return and A calls D. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  10. Stacks (2) Use of an operand stack for doing an arithmetic computation. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  11. The IJVM Memory Model The various parts of the IJVM memory. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  12. The IJVM Instruction Set (1) The IJVM instruction set. The operands byte, const, and varnum are 1 byte. The operands disp, index, and offset are 2 bytes. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  13. The IJVM Instruction Set (2) • Memory before executing INVOKEVIRTUAL. • After executing it. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  14. The IJVM Instruction Set (3) • Memory before executing IRETURN. • After executing it. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  15. Compiling Java to IJVM (1) • A Java fragment. • The corresponding Java assembly language. • The IJVM program in hexadecimal. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  16. Compiling Java to IJVM (1) The stack after each instruction of Fig. 4-14(b). Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  17. Microinstructions and Notation All permitted operations. Any of the above operations may be extended by adding ‘‘<< 8’’ to them to shift the result left by 1 byte. For example, a common operation is H = MBR << 8 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  18. Implementation of IJVM Using the Mic-1 (1) The microprogram for the Mic-1 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  19. Implementation of IJVM Using the Mic-1 (2) The microprogram for the Mic-1 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  20. Implementation of IJVM Using the Mic-1 (3) The microprogram for the Mic-1 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  21. Implementation of IJVM Using the Mic-1 (4) The microprogram for the Mic-1 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  22. Implementation of IJVM Using the Mic-1 (5) The microprogram for the Mic-1 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  23. Implementation of IJVM Using the Mic-1 (6) The BIPUSH instruction format. • ILOAD with a 1-byte index. • WIDE ILOAD with a 2-byte index. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  24. Implementation of IJVM Using the Mic-1 (7) The initial microinstruction sequence for ILOAD and WIDE ILOAD. The addresses are examples. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  25. Implementation of IJVM Using the Mic-1 (8) The IINC instruction has two different operand fields. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  26. Implementation of IJVM Using the Mic-1 (9) The situation at the start of various microinstructions. a) Main1. b) goto1. c) goto2. d) goto3. e) goto4. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  27. Speed Versus Cost • Reduce the number of clock cycles needed to execute an instruction. • Simplify the organization so that the clock cycle can be shorter. • Overlap the execution of instructions. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  28. Merging the Interpreter Loop with the Microcode (1) Original microprogram sequence for executing POP. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  29. Merging the Interpreter Loop with the Microcode (2) Enhanced microprogram sequence for executing POP. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  30. A Three Bus Architecture (1) Mic-1 code for executing ILOAD. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  31. A Three Bus Architecture (2) Three-bus code for executing ILOAD. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  32. A Three Bus Architecture (3) A fetch unit for the Mic-1. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  33. A Three Bus Architecture (4) A finite state machine for implementing the IFU. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  34. A Three Bus Architecture (5) The data path for Mic-2. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  35. A Pipelined Design: The Mic-3 (1) The microprogram for the Mic-2 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  36. A Pipelined Design: The Mic-3 (2) The microprogram for the Mic-2 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  37. A Pipelined Design: The Mic-3 (3) The microprogram for the Mic-2 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  38. A Pipelined Design: The Mic-3 (4) The microprogram for the Mic-2 Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  39. Three BusArchitecture The three-bus data path used in the Mic-3. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  40. Implementation of SWAP (1) The Mic-2 code for SWAP. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  41. Implementation of SWAP (2) The implementation of SWAP on the Mic-3. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  42. Pipeline Graphical illustration of how a pipeline works. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  43. A Seven-Stage Pipeline: The Mic-4 (1) The main components of the Mic-4. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  44. A Seven-Stage Pipeline: The Mic-4 (2) The Mic-4 pipeline. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  45. Cache Memory A system with three levels of cache. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  46. Direct-Mapped Caches (a) A direct-mapped cache. (b) A 32-bit virtual address. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  47. Set-Associative Caches A four-way set-associative cache. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  48. Branch Prediction (a) A program fragment. (b) Its translation to a generic assemblylanguage. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  49. Dynamic Branch Prediction (1) (a) A 1-bit branch history. (b) A 2-bit branch history. (c) A mapping between branch instruction address and target address. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

  50. Dynamic Branch Prediction (2) A 2-bit finite-state machine for branch prediction. Tanenbaum, Structured Computer Organization, Fifth Edition, (c) 2006 Pearson Education, Inc. All rights reserved. 0-13-148521-0

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