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Structure of Computer Systems

Structure of Computer Systems. Course 8 Memory system. Memory – as main component of a von Neumann computer. Role: stores instruction codes and data Basic types: registers - contained in the CPU

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Structure of Computer Systems

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  1. Structure of Computer Systems Course 8 Memory system

  2. Memory – as main component of a von Neumann computer • Role: • stores instruction codes and data • Basic types: • registers - contained in the CPU • register types: general purpose registers, instruction register, program counter, stack pointer, control and status registers • access – direct through internal links or buses • access time – 1 clock period or less • internal or main memory • access: through the system bus – read/write transfer cycles • random access to every location, based on the location’s address • technology: semiconductor circuits • access time: 1—70ns • external memory • indirectly accessible through interfaces and system bus • sequential or partially random access to blocks of memory (e.g. sectors) • technology: magnetic , optical, semiconductor • access time: 0.1-10ms

  3. Memory system • New memory types: • Cache memory • high-speed low capacity memory between the CPU and the internal memory • keeps copies of the main memory’s zones (lines) • Virtual memory • extension of the internal memory on the external memory • mechanisms for protecting memory zones allocated for different purposes • Memory hierarchy = • cache memory • internal memory • virtual memory

  4. Memory technologies (semiconductor technologies) • Basic classification: • ROM • non-volatile memory • types: ROM, PROM, EPROM, EEPROM, Flash • RAM • volatile memory • types: • Static RAM (SRAM): • bipolar, CMOS • Dynamic RAM (DRAM) • (basic) DRAM, FPM DRAM, EDRAM, SDRAM, DDRAM1, 2, 3, RAMBUS-DRAM

  5. Memory design issues • Access: • address-based: • random – every location can be accessed randomly based on its address (e.g. RAM, ROM) • sequential – the locations are read or written one after the other (magnetic tape, CCD – charge coupled devices) • partial random – random at block level (e.g. sector) and sequential inside a memory block (e.g. magnetic and optical disk) • associative – a location is found based on a tag (content) associated to every location • stack – a location is found on top of the stack – the stack pointer is automatically incremented or decremented for read and write operations • Volatility: • non-volatile memories – does not lose their content when the power is switched off (e.g. ROM, PROM, EEPROM, Flash) • volatile memories – lose their content without power supply • static memories – preserve the data as long as the circuit has power supply • dynamic memories – lose their content in time (e.g. DRAMs) even if power is ON - requires periodic refresh cycles

  6. Memory design issues • communication: • through a parallel bus – address, data and control signals • asynchronous bus – classical bus controlled through control signals (e.g. 8086 bus) • synchronous bus – controlled through the clock signal (e.g. P6 bus) • through a serial bus – serial transmission based on a protocol (e.g. SPI, I2C) • trough an interface – indirect access (e.g. hard-disc interface) • organization: • uniform access – every location accessed in the same way • non-uniform memory access (NUMA) – access depends on the position of the memory relative to a given CPU

  7. Memory system – basic concepts • memory cell • smallest storing unit • preserves 1 logical variable – 1 bit (binary digit) • usually, not directly accessible • implementations: • flip-flop (2,4, 6 transistors) - SRAM • a condenser (1 CMOS transistor) – DRAM • conductor/isolator – ROM, PROM, EPROM EEPROM • magnetic polarization – magnetic disc • transparent/opaque surface – optical disc • memory location • a group of memory cells (8, 16, 32 bits) addressable as an individual • addressing: unique address, incremental or sequential, associative • a memory location has: • an address and • a content

  8. T sel/W sel Vcc sel D D sel/R SRAM T1 seli DRAM sel F PL T  T2 T1 D D T2 D T3 C PROM EPROM D ROM Memory system – basic concepts • Examples of memory cells

  9. .... Address 0 1 2 3 4 5 ..FFD ..FFE ..FFF Dm Dm-1 Dm-2 ... D0 one location Columns 1 2 3 4 ..FF .... .... .... .... .... .... 0 1 Lines 2 3 1 ..FF Memory system – basic concepts • memory structure (block) • linear organization – locations placed one after the other at ascending addresses • matrix organization – a location is at the intersection of a line and a column Dm Dm-1 Dm-2 ... D0 one location

  10. Sel0 Data Amp Sel1 Data D0-Dm DEC Memory locations Address A0-An ... Sel Chip select CS Dir Write signal Wr or program Control unit OE Memory system – basic concepts • Memory structure • internal structure of a ROM or SRAM memory circuit • Components • address decoder • memory locations • data amplifier • control unit

  11. Read Memory Cycle A0-An valid address CS Wr valid data D0-Dm taccess tcycle Write Memory Cycle valid address A0-An CS Wr valid data D0-Dm taccess tcycle Memory system – basic concepts • Time diagrams for memory read and memory write cycles

  12. Column RAW addr RAW addr buf RAW DEC RAW Address Col addr buf Column addr DATA MUX RAS Control unit CAS Din Dout Memory system – basic concepts • Memory structure • internal structure of a DRAM memory circuit

  13. Memory system – basic concepts • DRAM memory: • Components: • raw and column address buffers • raw address decoder • column data multiplexer • memory locations • control unit • Issues • too many address lines • memory must be refreshed raw by raw • Solutions: • address lines are multiplexed in time (half of the address pins are needed) • two extra selection signals: • RAS – Raw address select • CAS – Column address select • no chip select line • external refresh cycles

  14. Memory Read Cycle A0-An/2 Raw Column RAS CAS Wr valid data D0-Dm taccess tcycle Memory system – basic concepts • Time diagram for DRAM memory read cycle

  15. Memory Write Cycle A0-An/2 Raw Column RAS CAS Wr valid data D0-Dm taccess tcycle Memory system – basic concepts • Time diagram for DRAM memory write cycle

  16. Memory system – basic concepts • Time diagram for DRAM memory refresh cycle Memory Refresh Cycle A0-An/2 Raw RAS CAS Wr D0-Dm tcycle

  17. Memory system – basic concepts • Access time • one of the most important parameter of a memory circuit • measures the time required to perform a read or write operation • measured from the moment when address lines are stable until the data is read or written in the memory • smaller access time => higher speed • taccess = taddr_dec + tcell_read/write + ten_amp depends on capacity constant for a technology enable/disable time

  18. Memory system – basic concepts • Access time (cont) • depends on technology • ROM – medium – 20-30 ns • SRAM – small – 10-15ns • DRAM – high – 70ns (basic DRAM); 10-15ns (DDRAM – block read) • Read/write cycle period • minimum time needed to perform a complete read or a write operation • measured from the moment address signals are stable until the address and data lines may be disabled • Technology dependences: • constant time for SRAM, ROM; variable for DRAM (see refresh) • same for read and write – SRAM, DRAM; write is much longer – Flash, EEPROM

  19. Memory system – basic concepts • Memory capacity • number of locations or bytes • measured in kilo (k), mega (M), giga (G) or terra (T) locations or bytes • capacity is dependent of technology • ROM, SRAM technologies: • small capacity/chip – 64KB-4MB • flash – 4-64GB • DRAM technologies: • high capacity/chip – 2-8 GB

  20. New DRAM technologies • Why DRAM memories? • very big capacity/chip (1-4GB) at a reasonable price • SRAMs cannot be implemented at such capacities • Problems with DRAMs: • require periodic refresh cycles • address multiplexing • too long access time (70ns) • Conclusions: • most of today’s computers use DRAM circuits as their main memory • we have to do something to reduce the access time and to reduce the impact of extra refresh cycles

  21. A0-An/2 Raw Col1 Col2 Col3 Col4 RAS CAS Wr D0-Dm data1 data2 data3 data4 taccess taccess taccess taccess No delay for EDO-DRAM New DRAM technologies • FPM-DRAM • idea – one raw address and multiple column addresses – sequential block read/write: • data1,2,4 – read; data3 – write

  22. New DRAM technologies • EDO-DRAM – Enable Data Output DRAM • an extra output enable signal (OE) that eliminate the delay between two consecutive columns (see previous diagram) • BEDO-DRAM Burst EDO-DRAM • consecutive column addresses are generated inside the memory chip (no extra CAS cycles are needed)

  23. New DRAM technologies • SDRAM – synchronous DRAM • synchronous mode; every signal controlled by the processor’s clock signal • memory organized on blocks that can work in parallel • promotes burst data transfers (1,2,4, 8 or a whole page) • pipelined access to the memory; a new access may be initiated before the previous ended • consecutive addresses generated inside the memory chip • access time is 4 times smaller than classic DRAM

  24. Clock Command Read Nop Nop Nop Read Nop Nop Address Data Dn Dn+1 Dn+2 Dn+3 Dm taccess Block n Block m New DRAM technologies • SDRAM – synchronous DRAM (cont.)

  25. New DRAM technologies • DDR – SDRAM – Double Data Rate SDRAM • makes data transfer on both edges of the clock signal (double pumping) – reduces the required clock frequency to half • very strict timing conditions • 64 bit transfers

  26. Design of memory modules • Design parameters: • capacity: • in number of locations or bytes • organization: • bits/location • addressing: random, sequential addressing (FIFO, LIFO), associative • bus specifications: • address and data signs • control signals • timing (time diagrams) • starting address: • place of the designed module in the addressing space of the processor • available circuits • special requirements (e.g. refresh, periodic access, etc.)

  27. Design of ROM or SRAM memory modules • Steps: • build a sub-module with the required data width • build the memory matrix • design the address decoder • address amplifiers • data amplifiers • control unit (if necessary)

  28. Sel Metrix of memory circuites Data Amp. Data Addresses sig Address Amp. Module selection Control circuit Dec Command sig. Design of a SRAM memory modules • Design parameters: • Capacity: 1Mbytes • Organization: 16 bits with access on 8 bits too • The bus: • ISA (24 address lines, 16 data lines, MRDC, MWTC) • Start address: C0000H • Available circuits: 64Kbytes

  29. A1 A2 D0 64K*8 D1 A16 D7 WR\ CSLi\ D8 64K*8 D9 D15 CSHi\ Submodule 64K*16= 128K*8 Building a sub-module with the required data width

  30. A1-A16 64K*16 D0-D15 WR\ CSL0\ CSH0\ 64K*16 CSL1\ CSH1\ … 64K*16 CSL7\ 512K*16=1M*8 CSH7\ Building the memory matrix with the required capacity

  31. Design of the decoder unit A17-A23 CS0\ DEC DEC CS1\ CS7\ MRDC\, MWTC\ SelMod\ BHE\ A0 A23 CSL0\ A17 74LS138 A22 A18 A21 A19 CSH0\ A20 CSL7\ MRDC\ MWTC\ CSH7\ SelMod\

  32. Design of address and data amplifiers SA0 A0 74LS244 SA1 A1 SA7 A7 SD0 D0 74LS245 SD1 D1 SD7 D7 RD\ SelMod\ SA8 A8 SA9 A9 74LS244 SA15 A15 SD8 D8 74LS245 SD9 D9 SD15 D15 SA16 A16 74LS244 SA23 A23

  33. Design of a DRAM memory module Address bus Data bus MUX MUX Amp 2:1 2:1 DRAM Refresh RAS W Counter AdrSel CAS WR \ CAS0 \ ,CAS1 \ ,….CASn MRD \ Command RAS \ device CAS \ MWR \ CSM \ Oscilator RefReq DEC. CS0 \ , CS1 \ , ..CSn

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