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Understanding Mealy and Moore FSMs: State Variants and Circuit Design

This chapter explores finite state machines (FSMs) with a focus on Mealy and Moore models. It highlights the key differences in output behavior, where Moore FSM outputs depend solely on the current state, whereas Mealy FSM outputs depend on both the current state and input signals. The chapter includes detailed diagrams and circuit designs, clock cycle analysis, truth tables, and examples of counting sequences. Additionally, it discusses potential synchronization issues when connecting outputs to other circuits. Homework assignments reinforce understanding of FSM design.

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Understanding Mealy and Moore FSMs: State Variants and Circuit Design

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  1. Chapter 8 continued Mealy FSMs

  2. FSM Model Variants • Moore-type • Outputs depend only on Present State • Mealy-type • Outputs depend on Present State AND Inputs

  3. Specify Desired Circuit • One input w • One output z • All changes occur on positive edge of clock • Output z = 1 if • During immediately preceding clock cycle the input w was equal to 1 AND is currently equal to 1 • Output z = 0 otherwise Clockcycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0

  4. New Machine Clockcycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0 Old Machine Clockcycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 0 1 0 0 1 1 0

  5. Clockcycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0 A A clk w z Reset ¤ w = 0 z = 0 A

  6. Clockcycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0 A A B clk w z Reset ¤ w = 1 z = 0 ¤ w = 0 z = 0 A B

  7. Clockcycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0 A A B A clk w z Reset ¤ w = 1 z = 0 ¤ w = 0 z = 0 A B ¤ w = 0 z = 0

  8. Clockcycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0 A A B A B clk w z Reset ¤ w = 1 z = 0 ¤ ¤ w = 0 z = 0 w = 1 z = 1 A B ¤ w = 0 z = 0

  9. Clockcycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0 A A B A B B clk w z Reset ¤ w = 1 z = 0 ¤ ¤ w = 0 z = 0 w = 1 z = 1 A B ¤ w = 0 z = 0

  10. Clockcycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0 A A B A B B A clk w z Reset ¤ w = 1 z = 0 ¤ ¤ w = 0 z = 0 w = 1 z = 1 A B ¤ w = 0 z = 0

  11. Clockcycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0 A A B A B B A B clk w z Reset ¤ w = 1 z = 0 ¤ ¤ w = 0 z = 0 w = 1 z = 1 A B ¤ w = 0 z = 0

  12. Clockcycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0 A A B A B B A B B clk w z Reset ¤ w = 1 z = 0 ¤ ¤ w = 0 z = 0 w = 1 z = 1 A B ¤ w = 0 z = 0

  13. Clockcycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0 A A B A B B A B B B clk w z Reset ¤ w = 1 z = 0 ¤ ¤ w = 0 z = 0 w = 1 z = 1 A B ¤ w = 0 z = 0

  14. Clockcycle: t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10 w : 0 1 0 1 1 0 1 1 1 0 1 z : 0 0 0 0 1 0 0 1 1 0 0 A A B A B B A B B B A clk w z Reset ¤ w = 1 z = 0 ¤ ¤ w = 0 z = 0 w = 1 z = 1 A B ¤ w = 0 z = 0 During present clock cycle output value on arc from Present State node Note difference from Moore model in where output is shown output changes asynchronously

  15. z Next state Output Present state w = 0 w = 1 w = 0 w = 1 A A B 0 0 B A B 0 1 State Table & State Assignment Next state Output Present state w = 0 w = 1 w = 0 w = 1 y Y Y z z A 0 0 1 0 0 B 1 0 1 0 1

  16. Derivation of Next-state and Output Expressions Next state Output Present state w = 0 w = 1 w = 0 w = 1 y Y Y z z A 0 0 1 0 0 B 1 0 1 0 1 Y Truth Table y w Y 0 0 0 0 1 1 1 0 0 1 1 1 z Truth Table y w z 0 0 0 0 1 0 1 0 0 1 1 1 Y = w z = y.w

  17. Asynchronous Behavior of Mealy Model • If z is connected to another synchronous clock no problem • If z is connected to another circuit not controlled by the same clock a potential problem exists

  18. Analysis of Synchronous State Machines

  19. Next State Present Output How many states? Create Present State/Next State/Output table state z

  20. Next State Present Output state w = 0 w = 1 z y y 2 1 Y Y Y Y 2 1 2 1 0 0 0 0 01 0 0 1 0 0 10 0 1 0 0 0 11 0 1 1 0 0 11 1

  21. Counter Using Sequential State Machine • Counting Sequence is 0,1,2,…,6,7,0,1,… • Input w • If w = 0 present count remains the same • If w = 1 count is incremented • Create State Diagram • Create State Table • Create State Assignments

  22. FSM with Two Inputs • Inputs w1 and w2 • Outputs z • If w1 = w2 during any four consecutive clock cycles z = 1 • Otherwise z = 0 w1 0 1 1 0 1 1 1 0 0 0 1 1 0 w2 1 1 1 0 1 0 1 0 0 0 1 1 1 z 0 0 0 0 1 0 0 0 0 1 1 1 0

  23. Homework • Brown 8.3 & 8.5 • Create • State Diagram • State Table • State Assignment Table

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