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MAC Controller Implementation

MAC Controller Implementation. Delta Network ASIC Division Project Manager Roger Lin. Content. Project Initialization System Specification Data Flow ASIC Specification ASIC Block Diagram Implementation Target Design Flow. Content. Interface Definition MAC Controller Sub-Block

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MAC Controller Implementation

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  1. MAC Controller Implementation Delta Network ASIC Division Project Manager Roger Lin

  2. Content • Project Initialization • System Specification • Data Flow • ASIC Specification • ASIC Block Diagram • Implementation Target • Design Flow

  3. Content • Interface Definition • MAC Controller Sub-Block • Design Phase • Synthesis Phase • Backend Phase • System Engineering

  4. Project Initialization • Target : Ethernet Switch • Evolve from Multi-port Bridge • Kapana Network • Market v.s. Technical • Information Re-assembly • International Showcase • DataBook • Standards

  5. Internet Product Hierarchic Intranet Bridge Router TP-HUB

  6. Application Trend • Standalone Computer Process • Database Share Localization • Centralize Information Maintain • Internet Access • Remote Branch Office Handle • E-Commerce

  7. Multi-port Bridge High-End RISC CPU SRAM SRAM SRAM EEPROM CAM Serial Port MAC Controller MAC Controller MAC Controller MAC Controller PHY ChipSet PHY ChipSet PHY ChipSet PHY ChipSet RJ-45 BNC RJ-45 RJ-45

  8. System Specification • Same with Multi-port Bridge • 802.3 MAC • 802.1D Bridging • Switching Technology • Hardware Forward • Cut Through/Store and Forward • Unique Media Access

  9. Media Access Control • Ethernet/802.3 • Token Ring • Token Bus • FDDI LLC 802.3 Token Bus Token Ring FDDI 10B2 10B5 TP

  10. Ethernet/802.3 Receive Transmit Rx done ? Defer on ? Y Send jam Y Frame Small ? (Col) Start Tx Y Increment attempts Valid FCS ? Defer on ? Y Y Recog addr ? Defer on ? Y Extra bits ? Y Valid Lengh Field ? Tx done ? Compute Backoff Y Y Y Wait backoff time Done: Align Error Done: OK Done: OK Done: excessiveColError Done: FCS Error Done: Length Error

  11. RELAY MAC MAC PHY PHY B B 802.1D Bridging • Forwarding • Outgoing Port • Learning • Host Location • Database • Network Topology • Spanning Tree • solve loop

  12. Ethernet Switch System Block Low-End CPU SRAM EEPROM Serial Port Switching Fabric SRAM MAC Controller SRAM MAC Controller SRAM MAC Controller SRAM MAC Controller PHY ChipSet PHY ChipSet PHY ChipSet PHY ChipSet RJ-45 BNC RJ-45 RJ-45

  13. Data Flow • Multi-port Bridge • Concentrate on the High-End CPU • Compute and Move Data by CPU • Ethernet Switch • Multiple Channel in Switch Fabric • Dynamic Connect by Hardware

  14. ASIC Specification • New MAC Controller • Major Function of CSMA/CD • Major Function of Bridging • Interface with Switch Fabric • Switch Fabric • Crossbar • Share Bus • Share Memory

  15. New MAC Block Diagram Memory Access Interface To Switch Interface From Switch Interface CPU Interface Controller Packet Buffer Read Controller Packet Buffer Write Controller Bridging Function Controller Packet Buffer Write Controller Packet Buffer Read Controller 802.3 Receive Controller 802.3 Transmit Controller Carrier Handle Controller

  16. ASIC Block Diagram • Separate MAC Controller Module • Easy to Re-use/Replace • Mirror Packet Buffer Controller • Reduce the Corner Case • Separate Bridging Controller • Easy to Upgrade to Layer 3 Operation

  17. Implementation Target • FPGA v.s. ASIC • Low Development Cost • Short Time-to-Market • Easy to Debug • Bad Timing Budget • More Effort to Partition • Proprietary “Generic Logic Block” • Difficult to Estimate

  18. Design Flow Easy to Maintain, Re-use and Expand Critical point to Success HDL Coding Functional Verification Library Survey Synthesis First Step for Link-to-Layout FloorPlan Toggle Rate for pattern driven, STA for Synchronous Design Pre-Simulation Static Timing Analysis Layout Post-Simulation (STA)

  19. 802.3 Receive ControllerHighlights • Collision Handle • Collision Drop • Late Collision to CPU • Physical Layer Error Handle - Drop • Runt Frame Handle - to Packet Buffer • Long Frame Handle - to Packet Buffer • Frame Check Sum Error Handle - Drop

  20. 802.3 Receive ControllerHighlights • Alignment Error Handle - Drop • Clock Synchronization • Lose by Packet Alignment • Wire Speed Receive • Interface with Packet Buffer Controller

  21. 802.3 Transmit ControllerHighlights • Collision Handle • Re-transmit Function • Skip Transmit Function • Jam Function • Backoff Function • [0, 2ek) where k = min (n, 10) • Defer Function

  22. 802.3 Transmit ControllerHighlights • Wire Speed Transmit • Clock Synchronization

  23. Interface Definition 802.3 Receive Controller DATA[7:0] Packet Buffer Write Controller DATA_VALID DATA_END DATA_ERR 802.3 Transmit Controller Packet Buffer Read Controller TXD[7:0] TXS[1:0] TXACK[1:0]

  24. Interface Definition - RX MII[3:0] Network Data Payload DATA[7:0] DATA_VALID DATA_END MII[3:0] Network Data Payload DATA[7:0] DATA_VALID DATA_ERR

  25. Interface Definition - TX MII[3:0] Network Data Payload TXD[7:0] TXS[1:0] Valid Idle Valid End TXACK[1:0] Valid Idle Valid Idle Valid MII[3:0] Network Data Payload TXD[7:0] TXS[1:0] Valid Idle Valid Idle TXACK[1:0] Valid Idle Re/Sk Idle

  26. RX/TX Block Diagram Statistic Counter To Packet Buffer Write Interface Interface Command Decoder Phy Management Byte to Word Word to Byte FIFO Clock Synchronization Defer CRC Check Nibble to Word MII TX Controller Backoff Carrier Handle Controller

  27. Design Phase • Clock Domain Partition • Meta Stable • State Machine • Merely • Moore • One-hot • Combinational • Product Term

  28. Design Phase • Naming Rule • Exclusion Logic • Datapath Sharing • Power Consumption • FlipFlop • Gated Clock • State Bit Transition

  29. tx_ctrl tx_ctrl ( .txack(txack[1:0]), .data_shift(data_shift), .pre_end(pre_end), .vartest4(vartest4), .txs(txs[1:0]), .fifo_full(fifo_full), .err(err), .retx(retx), .montx(montx), .CP(CP), //load 3 .NC(NC) ); tx_write tx_write ( .tx_cmd_write(tx_cmd_write), .vartest5(vartest5), .data_shift(data_shift), .endtag(tx_cmd_data[8]), .full(fifo_full), .err(err), .CP(CP), //load 3 .NC(NC) ); dffex8 DFFEx8_1( .Q(bus1[7:0]), .QN(), .D(txd[7:0]), .E(data_shift), .NC(NC), .CP(CP) //load 8 ); dffex9 DFFEx9_2( .Q(tx_cmd_data[8:0]), .QN(), .D({pre_end, bus1[7:0]}), .E(data_shift), .NC(NC), .CP(CP) //load 8 );

  30. assign vartest4 = {data_shift, stateQ}; assign txack[1] = (stateQ == x_start) //idle | (stateQ == x_valid) //valid | (stateQ == x_err) //idle | (stateQ == x_idle), //idle txack[0] = (stateQ == x_start) | (stateQ == x_err) //idle | (stateQ == x_idle) | (stateQ == x_sktx), pre_end = (txs == 2'b01) & (txack == 2'b10), data_shift = ((txs == 2'b10) | (txs == 2'b01)) & (txack == 2'b10) & (stateQ == x_valid); always @( txs or fifo_full or err or retx or montx or stateQ ) begin stateD = stateQ; case (stateQ) // synopsys parallel_case x_start : if (txs == 2'b10 & montx & ~err & ~fifo_full) stateD = x_valid; x_valid : if (err) stateD = x_err; else if (txs == 2'b01) stateD = x_start; else if (fifo_full) stateD = x_idle;

  31. x_idle : if (~fifo_full) stateD = x_valid; x_err : if (retx) stateD = x_retx; else if (~retx) stateD = x_sktx; x_retx : stateD = x_start; x_sktx : stateD = x_start; default : stateD = x_start; endcase end //----------------------FLIP FLOP AREA------------------ always @( posedge CP or negedge NC ) begin if (~NC) stateQ[2:0] = #2 3'h0; else stateQ[2:0] = #2 stateD[2:0]; end //DFFC_d1 DFF0 (.Q(stateQ[0]), .D(stateD[0]), .CP(CP), .NC(NC)); //DFFC_d1 DFF1 (.Q(stateQ[1]), .D(stateD[1]), .CP(CP), .NC(NC)); //DFFC_d1 DFF2 (.Q(stateQ[2]), .D(stateD[2]), .CP(CP), .NC(NC));

  32. Synthesis Phase • Strategy • Bottom Up • Synthesis - Characterize - Re-synthesis • Critical Path • Fine Tune Constraint • Register Re-timing • Re-code RTL

  33. Backend Phase • Floor Plan • ECO ( Engineering Change Order ) • Clock Skew • Layout Density

  34. System Engineering • Test Environment • Q & A

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