Power-aware NOC Reuse on the Testing of Core-based Systems*

1. Power-aware NOC Reuse on the Testing of Core-based Systems* CSCE 932 Class Presentation by Xinwang Zhang April 26, 2007 * Erika Cota, et al., International Test Conference, 2003

2. Outline • Researching background and motivation • NOC reuse on the testing • Power-Aware NOC reuse during test • Experimental result • BISTed Cores and Power-aware NOC Reuse Power-aware NoC Reuse

3. Researching Background and Motivation • Reuse functional connections during test. (M. Nourani, et, 1998-2002) • Use packet-switching architecture. No power consumption is modeled. (NIMA) (Aktouf and Nahvi) • Introduce power constraints. Two cores are not tested concurrently if the sum of their power consumption is larger than the maximum value. (R. M. Chou and E. Larsson) • Power profile manipulation approach for the minimization of the power dissipation and test time during test. (Rosinger, et al, 2002) Power-aware NoC Reuse

4. NOC reuse on the testing • SOC Interconnection Network (SOCIN) • XY routing • Packet-switched • Wormhole switching approach (flits, the smallest unit, follow the header in a pipeline way. Its size equals the channel width) Power-aware NoC Reuse

5. NOC reuse on the testing • Test vector and test response of each core are expressed as two packets, divided into a number of flits. • Wrapper configuration, two modes. In the test mode, in order to ensure each flit is unpacked in the same time. The scan chains, input and output should be similar length. • Control information is also carried by specific bits in packets Power-aware NoC Reuse

6. NOC reuse on the testing • For core (3, 4 and 8), the same number of flits per packet is used. The reason is the number of scan chains and input, output is less than 16. Power-aware NoC Reuse

7. NOC reuse on the testing • Timing conflict problem: multiple paths are transmitting/receiving packets. The order of input packet and output packet. • Solution: 1. Each core has two scheduling times. (Next vector can be delivered, next response can be delivered) 2. Give each channel a time information. (Free or not) Power-aware NoC Reuse

8. NOC reuse on the testing • The priority of using a given path. The cores with larger number and larger size of packets have priority to use shorter paths to reduce test time. • Test cost computation: Power-aware NoC Reuse

9. Power-Aware NOC reuse during test • Main advantage: the possibility of parallelization provided by NOC. • Disadvantage: More cores are tested in parallel more power consumption. • Four sources of power consumption: router, channel, core and wrapper. Power-aware NoC Reuse

10. Power Consumption Calculation • Router: • Channel: • Total power consumption for a packet transmission: • Suppose core’s and wrapper’s power consumption is given by core designer. Power-aware NoC Reuse

11. Power-aware test scheduling • Test schedule: defined as a set of time slots of different lengths. • Size of time slot: clock cycles • Each slot contains a set of packets • One packet transmission may be distributed among several slots • Slots can be modified as the schedule is being defined. • Total power consumption in one slot: • The system power limit must be respected at each time slot s: Power-aware NoC Reuse

12. Power-aware test scheduling • The scheduling of a packet V of core 6. Power-aware NoC Reuse

13. Experiment Results • Power consumption limit was defined as a certain percentage of the sum of the power consumption of all cores. (system requirement). • Circuit used in the experiment: d695, g1023, p22810 • The variation of the system test time according to: the maximum test power consumption, and the number of system interfaces. Power-aware NoC Reuse

14. Experiment Results Power-aware NoC Reuse

15. Experiment Conclusion • Power constrains can change the original order of the scheduled cores, leading the scheduling heuristic to a better solution in some particular cases. • Very tight power constraints may either increase the time or prevent the scheduling of the some test packets • The more interfaces with the tester, the higher the impact of the power constraints on the system test time. • Although one can notice an increase in the test time caused by power constraints, the network still presents a very effective trade-off in terms of pins and area overhead and test time. Power-aware NoC Reuse

16. BISTed Cores and Power-aware NOC Reuse • Advantage: only two messages that must transit: a test enable and the resulting signature. • Disadvantage: Larger number of test patterns, and higher power consumption Power-aware NoC Reuse

17. Power-aware NoC Reuse