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Data Storage VHDL ET062G & ET063G Lecture 4 Najeem Lawal 2012

Data Storage VHDL ET062G & ET063G Lecture 4 Najeem Lawal 2012. Data storage. Outline Counters Shift registers Memories Generate Generics Error management Line Buffers. Counters in VHDL.

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Data Storage VHDL ET062G & ET063G Lecture 4 Najeem Lawal 2012

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  1. Data Storage VHDL ET062G & ET063G Lecture 4 Najeem Lawal 2012

  2. Data storage • Outline • Counters • Shift registers • Memories • Generate • Generics • Error management • Line Buffers VHDL ET062G & ET063G Lecture 4

  3. Counters in VHDL library ieee;use ieee.std_logic_1164.ALL;use work.numeric_std.ALL;entity modulo256 ISPORT(clk: in std_logic; cnt: buffer unsigned (7 downto 0));END modulo256;architecture rtl of modulo256 isbeginprocess (clk)beginif rising_edge(clk) then cnt <= cnt +1;endifendprocess;end rtl; • Modulo-256 counter VHDL ET062G & ET063G Lecture 4

  4. d_in shift_out shift_en resetn Shift-register in VHDL architecturertlofshift_lis signalshift_reg: std_logic_vector(3 downto 0); begin process (clk, resetn) begin ifresetn = '0' then shift_reg <= (others=>'0'); elsifclk'eventandclk = '1' then ifshift_en='1' then shift_reg(3 downto 1)<=shift_reg(2 downto 0); -- shift_reg <= shl(shift_reg, "1"); -- shift_reg <= shift_regsll 1; shift_reg(0) <= d_in; end if; end if; end process; shift_out <= shift_reg; endrtl; library ieee;use ieee.std_logic_1164.ALL; entityshift_lis port ( clk, resetn, d_in, shift_en: instd_logic; shift_out:outstd_logic_vector(3 downto 0)); endshift_l; Alternative ways VHDL ET062G & ET063G Lecture 4

  5. Memories in VHDL • Memories occur as • Registers (signals, constants, variables or ports) • RAMs • ROMs • A RAM or ROM can be designed in two ways • Use the data-type array • Use a pre-defined macro cell for the memory device VHDL ET062G & ET063G Lecture 4

  6. Memories in VHDL • A RAM can be dual port or single port VHDL ET062G & ET063G Lecture 4

  7. Memories in VHDL • Address contention in dual port can be solved by specifying the order of execution for example, read first or write first. VHDL ET062G & ET063G Lecture 4

  8. Memories in VHDL • data path 1 writes to and read from Port A, • data path 2 write to and read from Port B, • data path 3 implements data transfer from Port A to Port B, • data path 4 implements data transfer from Port B to Port A. VHDL ET062G & ET063G Lecture 4

  9. Example: 48 ROM in VHDL libraryieee; use ieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entity ROM is port ( address : instd_logic_vector(1 downto 0); dout : outstd_logic_vector(7 downto 0)); end ROM; architecturertlof ROM is typerom_tableisarray (0 to 3) ofstd_logic_vector(7 downto 0); constantrom_contents : rom_table := rom_table'("00101111", "11010000", "01101010", "11101101"); begin -- rtl dout <= rom_contents(conv_integer(address)); endrtl; VHDL ET062G & ET063G Lecture 4

  10. RAM4_8 din q din dout a0 address0 a1 address1 we we Example #1: RAM in VHDL architecturertlofrmodulis component RAM4_8 port ( din: instd_logic_vector(7 downto 0), address0, address1, we : instd_logic; dout : outstd_logic_vector(7 downto 0); endcomponent; begin -- rtl ram1: RAM4_8 portmap ( din => d, address0 => a0, address1 => a1, we => we, dout => q); endrtl; Define existing RAM module existing in a library VHDL ET062G & ET063G Lecture 4

  11. RAM32_16 din dout addr we_n Example #2: RAM in VHDL libraryieee; use ieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entity ram32_16 is port ( addr : instd_logic_vector(4 downto 0); clk, we_n : instd_logic; din : instd_logic_vector(15 downto 0); dout : outstd_logic_vector(15 downto 0)); end ram32_16; VHDL ET062G & ET063G Lecture 4

  12. Example #2: RAM in VHDL architecturertlof ram32_16 is typeram_typeisarray (31 downto 0)ofstd_logic_vector(15 downto 0); signalram_array : ram_type; begin process(clk) begin ifclk'eventandclk='1' then ifwe_n='0' then ram_array(conv_integer(addr)) <= din; endif; end if; endprocess; dout <= ram_array(conv_integer(addr)); endrtl; Define an matrix VHDL ET062G & ET063G Lecture 4

  13. Generate Command in VHDL If the same component is to be instantiated many time in the same architecture, the generate command is the most effective approach Syntax: <g_Label> : FOR <loop_iteration> Generate <i_label >: <entity_name> port map ( <port-association-list> ); End generate <g_Label>; VHDL ET062G & ET063G Lecture 4

  14. Generate Command in VHDL • Using generate to create a 4-bit adder from 1-bit adder Entity adder_4bit is Port (a, b : in std_logic_vector(3 donwto 0); cin : in std_logic; sum : out std_logic_vector(3 downto 0); cout : out std_logic); End entity adder_4bit; VHDL ET062G & ET063G Lecture 4

  15. Generate Command in VHDL Architecture rtl of Adder_4bit is component adder_1bit port(a,b,cin : in std_logic; sum, cout : out std_logic); end component; Signal c_chain : std_logic_vector(4 downto 0); Begin c_chain(0) <= cin; cout <= c_chain(4); gen : for i in 0 to 3 generate u : adder_1bit port map (a(i), b(i), c_chain(i), sum(i), c_chain(i+1)); End architecture rtl; VHDL ET062G & ET063G Lecture 4

  16. Generate Command in VHDL ..... Begin c_chain(0) <= cin; cout <= c_chain(4); gen : for i in 0 to 3 generate u : adder_1bit port map ( a <=a(i), b <=b(i), cin <= c_chain(i), sum <= sum(i), cout <= c_chain(i+1)); End architecture rtl; VHDL ET062G & ET063G Lecture 4

  17. Generic Command • Generics • The generic statement declares constants that are analogous to arguments in functions in procedural programming. • These constants are set in the module that is hierarchically above the current one. • If they are not set, they take the default value that you give it. • Generic declarations are optional and their mapping. VHDL ET062G & ET063G Lecture 4

  18. Generic Command • Generics are used for • Timing: delays • Sizing: bus width • Limits: counter range • Syntax:<generic_name>: type [:= <initial_value>]; • Examples:bus_width: integer := 8;my_boolean: boolean := false; • DELAY: time :=5ns VHDL ET062G & ET063G Lecture 4

  19. Generic & Generate Command • How can we create a 64-bit adder • Or 128-bit or n-bit adder? • Where n > 0. • Hints: generics and Generate VHDL ET062G & ET063G Lecture 4

  20. Generic & Generate Command Entity adder_Nbit is Generic (N : integer := 100); Port (a, b : in std_logic_vector(N - 1 donwto 0); cin : in std_logic; sum : out std_logic_vector(N - 1 downto 0); cout : out std_logic); End entity adder_Nbit; Architecture rtl of Adder_Nbit is component adder_1bit port(a,b,cin : in std_logic; sum, cout : out std_logic); end component; Signal c_chain : std_logic_vector(4 downto 0); --..... VHDL ET062G & ET063G Lecture 4

  21. Generic & Generate Command --..... Begin c_chain(0) <= cin; cout <= c_chain(N); gen : for i in 0 to (N – 1) generate u : adder_1bit port map ( a <=a(i), b <=b(i), cin <= c_chain(i), sum <= sum(i), cout <= c_chain(i+1)); End architecture rtl; By combining generic and generate, it is possible to achieve a compact and variable number of construction. Here is an example of 100 bit adder. VHDL ET062G & ET063G Lecture 4

  22. Error Management in VHDL Assert statement Used to test constraint during simulation functional constraint time constraint If the condition is satisfied i.e. confirmed or asserted simulation continues If condition (functional or time) is not satisfied - print a report - specify the severity of the condition VHDL ET062G & ET063G Lecture 4

  23. Error Management in VHDL Assert statement Syntax: Assert <condition> Report <message> Severity <error_level> ; Message and Error Level are displayed in the simulator console as text. Assert statements can be both sequential and concurrent statements. Assert statements should only be in the test-benches because there are not synthesizable. VHDL ET062G & ET063G Lecture 4

  24. Error Management in VHDL Assert <condition> assert in /= '0' assert in1 /= '0' AND in2 = '1' assert now = 200 ns Report <message> report “Values of input in1 and in2 are invalid!” report “Simulation completed” report “Output x is out of range” VHDL ET062G & ET063G Lecture 4

  25. Error Management in VHDL Severity <error_level> severity Note Warning Error Failure VHDL ET062G & ET063G Lecture 4

  26. Error Management in VHDL architecture ex of assert_ex is begin assert a /= '1' or b /= '1' report “a='1' and b='1' at the same time!” severity Warning; P1 : process(a,b)‏ begin if a ='1' and b = '1' then assert false report “a='1' and b='1'”; end if end process P1; end architecture ex; Entity assert_ex is port ( a,b : in std_logic; q : out std_logic); end entity assert_ex; architecture ex of assert_ex is VHDL ET062G & ET063G Lecture 4

  27. Line buffers • Memories used to buffer a set of repitive data • Implemented as a read first then write block RAM • A First-In-First-Out shift register (FIFO) that can be implemented as a circular buffer • An example of a modulo-8 data set memory buffer VHDL ET062G & ET063G Lecture 4

  28. Line buffers • entity linebuffer is • generic ( • ADDR_WIDTH : integer := 10; • DATA_WIDTH : integer := 8; • WINDOW_SIZE : integer := 3; • ROW_BITS : integer := 9; • COL_BITS : integer := 10; • NO_OF_ROWS : integer := 480; • NO_OF_COLS : integer := 752 ); • port( • clk : in std_logic; • fsynch_in : in std_logic; • rsynch_in : in std_logic; • pdata_in : in std_logic_vector(DATA_WIDTH-1 downto 0); • fsynch_out : out std_logic; • rsynch_out : out std_logic; • pdata_out1 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out2 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out3 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out4 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out5 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out6 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out7 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out8 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out9 : out std_logic_vector(DATA_WIDTH -1 downto 0) ); • end linebuffer; VHDL ET062G & ET063G Lecture 4

  29. Line buffers • entity linebuffer is • generic ( • ADDR_WIDTH : integer := 10; • DATA_WIDTH : integer := 8; • WINDOW_SIZE : integer := 3; • ROW_BITS : integer := 9; • COL_BITS : integer := 10; • NO_OF_ROWS : integer := 480; • NO_OF_COLS : integer := 752 ); • port( ---..... ); • end linebuffer; VHDL ET062G & ET063G Lecture 4

  30. Line buffers • entity linebuffer is • generic (----....); • port( • clk : in std_logic; • fsynch_in : in std_logic; • rsynch_in : in std_logic; • pdata_in : in std_logic_vector(DATA_WIDTH-1 downto 0); • fsynch_out : out std_logic; • rsynch_out : out std_logic; • pdata_out1 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out2 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out3 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out4 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out5 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out6 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out7 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out8 : out std_logic_vector(DATA_WIDTH -1 downto 0); • pdata_out9 : out std_logic_vector(DATA_WIDTH -1 downto 0) ); • end linebuffer; VHDL ET062G & ET063G Lecture 4

  31. questions • About FPGA / VHDL • ABOUT VGA DISPLAY / timing • ABOUT IMAGE SENSOR timing • ABOUT RANGE SENSOR • About line buffers • About memories & counters VHDL ET062G & ET063G Lecture 4

  32. End of lecture 4 • Outline • Counters • Shift registers • Memories • Generate • Generics • Error management • Line Buffers VHDL ET062G & ET063G Lecture 4

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