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Wu, Jinyuan , Arden Warner Fermilab Oct. 2011

A Novel Digitization Scheme with FPGA-based TDC for Beam Loss Monitors Operating at Cryogenic Temperature. Wu, Jinyuan , Arden Warner Fermilab Oct. 2011. Typical Digitization Scheme for Recycling Integrators. Recycling Integrator. -. -. +. +. Counter. Q. T. I = N*Q/T.

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Wu, Jinyuan , Arden Warner Fermilab Oct. 2011

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  1. A Novel Digitization Scheme with FPGA-based TDC for Beam Loss Monitors Operating at Cryogenic Temperature Wu, Jinyuan, Arden Warner Fermilab Oct. 2011

  2. Typical Digitization Scheme for Recycling Integrators Recycling Integrator - - + + Counter Q T I = N*Q/T A Novel Digitization Scheme with FPGA TDC for BLM

  3. Not Too Many Pulses to Count A Novel Digitization Scheme with FPGA TDC for BLM

  4. Digitization Scheme Using TDC - - + + I = Q/dt dt Q TDC Recycling Integrator c0 c90 T Encoder c180 c270 A Novel Digitization Scheme with FPGA TDC for BLM

  5. TDC Implemented with FPGA A Novel Digitization Scheme with FPGA TDC for BLM

  6. Clock Domain Changing Multi-Sampling TDC in FPGA Multiple Sampling Q3 QF c0 c0 QE Q2 • Ultra low-cost. • Sampling rate: 250 MHz x4 phases = 1 GHz. • LSB = 1.0 ns. c90 QD Q1 c180 Q0 c90 c270 DV T0 T1 Trans. Detection & Encode 4Ch Coarse Time Counter TS Logic elements with non-critical timing are freely placed by the fitter of the compiler. This picture represent a placement in Cyclone FPGA A Novel Digitization Scheme with FPGA TDC for BLM

  7. The Sampling Portion of the 1 ns TDC A Novel Digitization Scheme with FPGA TDC for BLM

  8. The Simulation of the 1 ns TDC CK250 IN A Novel Digitization Scheme with FPGA TDC for BLM

  9. If You Want to Try: Larger System • The KAEN V1495 module is a trigger module with a Cyclone FPGA. • A firmware with 96 TDC channels plus trigger tables has been actually implemented. • For pure TDC, 128 channels can be fit into the FPGA. www.caen.it V1495 $3800+2*537 A Novel Digitization Scheme with FPGA TDC for BLM

  10. If You Want to Try: Small System Resolution: 40 ps (LSB) with Wave Union TDC Scheme Resolution: 0.7-1 ns (LSB) with Multi-Sampling Scheme www.altera.com THDB-H2G (HSMC to GPIO Daughter Board) $50 www.altera.com DK-START-3C25N Cyclone III FPGA Starter Kit $211 • The FPGA on the Starter Kit is fairly powerful. • More than 16 pairs LVDS I/O can be accessed via the daughter card. • FPGA can fit 32 channels but implementing 16 channels is more practical given the I/O pairs. • TDC data are stored in the RAM on the board and can be readout via USB. • A good solution for small experiment systems as well as student labs. A Novel Digitization Scheme with FPGA TDC for BLM

  11. Bench Top Measurements A Novel Digitization Scheme with FPGA TDC for BLM

  12. Cryogenic Ionization chamber 5k – 350K It is a helium-filled ionization chamber. It's current is proportional to the dose rate. ● The signal current is processed by a current to frequency converter to achieve a wide dynamic range and quick response dose rate excursions. ● All materials used are know to be radiation hard and suitable for operation at 5K. ● The electronics is self-contained and requires no computer to operate. A Novel Digitization Scheme with FPGA TDC for BLM

  13. Cryogenic Loss Monitor operation The chamber housing is held at negative potential and negative charge is collected on the center electrode. The HV is -95 V and is kept well below the minimum breakdown voltage of 156V in Helium. The electronics uses a recycling integrator as a current to frequency converter with a wide dynamic range. The charge per pulse is 1.63pC or 238µR at 1 atm (room temp) of He. The recycling integrator consist of a charge integrating amplifier with a 0.50 pF capacitance followed by a discriminator which senses when the capacitor is fully charged. The FPGA generates a fixed-width (1.2µs) discharge pulse with an amplitude of 3.3V. It connects to the amplifier input via a 13 MΩ resistor, creating a 254 nA discharge current A Novel Digitization Scheme with FPGA TDC for BLM

  14. Test Hardware NIM to LVDS Converter TDC Module A Novel Digitization Scheme with FPGA TDC for BLM

  15. Pulses at 150 nA A Novel Digitization Scheme with FPGA TDC for BLM

  16. Pulses at 300 nA A Novel Digitization Scheme with FPGA TDC for BLM

  17. Input Current and Output Pulses Input Current 100 nA/div Output Pulses A Novel Digitization Scheme with FPGA TDC for BLM

  18. Digitized Results I=Q/dt A Novel Digitization Scheme with FPGA TDC for BLM

  19. Beam Test: Magnet Sweeping Caused Beam Loss (100 s) • The test was performed in Fermilab A0 test facility. • A magnet was swept twice to induce some beam losses. • Beam losses are seen when the RF becomes on at 1 Hz. A Novel Digitization Scheme with FPGA TDC for BLM

  20. Beam Test: Magnet Sweeping Caused Beam Loss (20 s) • The first sweep is expanded as shown. • Beam losses are seen when the RF becomes on at 1 Hz. • No beam loss is seen when the magnetic field reaches “correct” values. A Novel Digitization Scheme with FPGA TDC for BLM

  21. Beam Test: Magnet Sweeping Caused Beam Loss (0.2 s) • Beam losses are seen when the RF becomes on at 1 Hz. • The ionization chamber responds the beam loss relatively rapidly. • The tail seems to be ion clean up process. A Novel Digitization Scheme with FPGA TDC for BLM

  22. Reducing Analog Design Challenges with Digital Tricks A Novel Digitization Scheme with FPGA TDC for BLM

  23. Pulse Width with Small & Large Current • When input current becomes large, the pulse width of the recycling integrator becomes large. • The charge in each pulse also increases. • It is easy to accommodate in digital processing. • No need to face analog challenges in integrator circuit. A Novel Digitization Scheme with FPGA TDC for BLM

  24. Digitization of both Leading Edge & Pulse Width CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 • Each hit contains 56 bits. • Leading edge is digitized at 1 ns LSB with 40 bits (>1000 s) full range. • Pulse width uses 16 bits to represent up to 65 ms. Leading Edge Time (40 bits) Pulse Width Leading Edge Time (40 bits) Pulse Width A Novel Digitization Scheme with FPGA TDC for BLM

  25. Self Zero-Suppression A Novel Digitization Scheme with FPGA TDC for BLM

  26. Self Zero-Suppression: No Beam Loss, No Data • There are less than 600 data points recorded in this time frame. A Novel Digitization Scheme with FPGA TDC for BLM

  27. Summary • Using FPGA TDC to digitize recycling integrator improves system performance: • Faster response: Promoting ionization chambers from long time dosimeters to fast beam protection instruments. • Reduced analog design challenge. • Self Zero-suppression. • The scheme is to be integrated into the real system. A Novel Digitization Scheme with FPGA TDC for BLM

  28. The End Thanks

  29. Pulse Width with Larger Input Current A Novel Digitization Scheme with FPGA TDC for BLM

  30. Suggestions • Can the leading edge of the discriminator be seen at the NIM port? • Will the output pulse width represent the charge pumped back? A Novel Digitization Scheme with FPGA TDC for BLM

  31. Possible Circuit • The width of the charge pulse signal is N*400 ns. In typical hysteresis setting with small input current, N is 3. When the input current is large, N could be 4 or larger. • The OUT2NIM signal is an OR of the discriminator input and the charge pulse signals. • Therefore, the leading edge of the NIM output represents the transition timing of the discriminator. • The measured width of the NIM pulse will be rounded to 400 ns, and this is proportional to the charge. A Novel Digitization Scheme with FPGA TDC for BLM

  32. TDC Using FPGA Logic Chain Delay • This scheme uses current FPGA technology  • Low cost chip family can be used. (e.g. EP2C8T144C6 $31.68)  • Fine TDC precision can be implemented in slow devices (e.g., 20 ps in a 400 MHz chip).  IN CLK A Novel Digitization Scheme with FPGA TDC for BLM

  33. FPGA TDC • A possible choice of the TDC can be a delay line based architecture called the Wave Union TDC implemented in FPGA. • Shown here is an ASIC-like implementation in a 144-pin device. • 18 Channels (16 regular channels + 2 timing reference channels). • This FPGA cost $28, $1.75/channel. (AD9222: $5.06/channel) • LSB ~ 60 ps. • RMS resolution < 25 ps. • Power consumption 1.3W, or 81 mW/channel. (AD9222: 90 mW/channel) A Novel Digitization Scheme with FPGA TDC for BLM Wave Union Launcher A In CLK

  34. - - Measurement Result for Wave Union TDC A • Plain TDC: • delta t RMS width: 40 ps. • 25 ps single hit. • Wave Union TDC A: • delta t RMS width: 25 ps. • 17 ps single hit. Raw TDC + LUT Histogram 53 MHz Separate Crystal Wave Union Histogram A Novel Digitization Scheme with FPGA TDC for BLM

  35. Differential Inputs and Ramping Reference Voltage - - + + TDC (Multi-Sampling) Recycling Integrator dt c0 c90 Encoder c180 N c270 A Novel Digitization Scheme with FPGA TDC for BLM

  36. The Top Layer of the 1 ns TDC A Novel Digitization Scheme with FPGA TDC for BLM

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