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The D Ø Silicon Track Trigger

The D Ø Silicon Track Trigger. http://www-d0.fnal.gov/trigger/stt. Bill Lee Florida State University 27 October 2003. Introduction + Motivation Design Status. The D Ø Run 2 Detector. New state of the art tracker and trigger. SMT. Level 1 Central Track Trigger. -.

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The D Ø Silicon Track Trigger

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  1. The DØ Silicon Track Trigger http://www-d0.fnal.gov/trigger/stt Bill Lee Florida State University 27 October 2003 • Introduction + Motivation • Design • Status

  2. The DØ Run 2 Detector New state of the art tracker and trigger SMT 27 October 2003

  3. Level 1 Central Track Trigger - • Custom hardware + firmware • Preprogrammed track equations matched to hit patterns • Sensitive to beam offsets beyond ~1mm from programmed beam spot • Installation complete, Still revising Firmware 27 October 2003

  4. The DØ Trigger System Crossing frequency 2.3MHz p p But data acquisition rate is limited to 50 Hz Þ 3 Level Trigger System L3 L2 L1 50 Hz 2.5 kHz 1 kHz Decision time 100ms Decision time ~50ms 2.3 MHz Decision time 4.2ms • Software based • Simple versions of reconstruction algorithms • Hardware based • Simple Signatures in each Sub-Detector • Software and Firmware based • Physics Objects e,,jets, tracks 27 October 2003

  5. B Decay Products Flight Length mm’s Collision Decay Vertex Impact Parameter The Idea • b quarks are key in many areas: • Higgs Physics (ZHbb) • top physics ( t->Wb) • B physics • b quarks have a finite lifetime • travel mm’s before they decay • displaced tracks • Would like to trigger on displaced tracks • using the precision of the Silicon Tracker • Impact parameter resolution 35 mm (includes 30 mm from beamspot) - - Tracks Need to make very fast decisions! 27 October 2003

  6. Physics Motivation for STT - • Increase inclusive bb production yield six-fold with low enough threshold to see Zbb signal • Control sample for b-jet energy calibration, bb mass resolution, b trigger and tagging efficiencies • Top quark physics • Factor of 2 improvement in top mass systematics due to improved jet energy scale calibration • Heavy bb resonances for Higgs searches • Double trigger efficiency for ZH(nn)(bb) by rejecting QCD gluons and light-quark jets • b-quark physics • Lower pT threshold on single lepton and dilepton triggers (BOmm, Bs mixing, etc.) • Increase BdoJ/Y KS yield by 50% (CP violation) • STT proposed 1998 as addendum to DØ baseline • Received approval and funding in 1999 - - - - - 27 October 2003

  7. road data Fiber Road Card SMT data Silicon Trigger Card Silicon Trigger Card Silicon Trigger Card Silicon Trigger Card Silicon Trigger Card Silicon Trigger Card Track Fit Card L2CTT Conceptual Design • L1CTTtracks in CFT • Define road in SMT • Select SMT hits in roads • Fit trajectory to L1CTT+SMT hits. Measure • pT, • impact parameter, • azimuth • Send results to L2 • Pass L1CTT information to L2 • Send SMT clusters to L3 27 October 2003

  8. STT components - • Fiber Road Card • receives and buffers road information from the CFT Level 1 trigger and broadcasts it to other cards • Receives SCL (trigger control) information • Controls buffering for L3 (BC) • Silicon Trigger Cards • find cluster centroids from SMT hits • match centroids to roads from FRC • Track Fit Card • fits tracks using STC clusters and CTT information (2 hits) • Sends track parameters to L2CTT/L2global • 2 SMT sectors/crate  6 crates 27 October 2003

  9. FRC STC STT Design L2 Global L2 Global to L2CTT SCL in to L2CTT CPU spare spare SBC terminator spare TFC STC STC STC STC STC STC STC STC TFC spare spare terminator 6 Identical Crates with 1 Fiber Road Card 9 Silicon Trigger Cards 2 Track Fit Cards 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Sector 1 Sector 2 Layout of Run 2A STT Crate 27 October 2003

  10. Contributing Institutions • Boston University • U. Heintz, M. Narain, E. Popkov (PD), L. Sonnenschein (PD), J. Wittlin (PD), K. Black (GS), S. Fatakia (GS), A. Zabi (GS), A. Das (GS), W. Earle (Eng), E. Hazen (Eng), S. Wu (Eng) • Columbia University • H. Evans, G. Steinbrück (PD), T. Bose (GS), A. Qi (Eng) • Florida State University • H. Wahl, H. Prosper, S. Linn, T. Adams, S. Blessing, W. M. Lee (PD), N. Buchanan (PD), S. Tentindo Repond (PD), S. Sengupta (GS), J. Lazoflores (GS), D. Kau (GS), R. Perry (Eng), S. Lolage (GS-Eng), V. Lalam (GS-ENG) • SUNY Stony Brook • J. Hobbs, W. Taylor (PD), H. Dong (GS), C. Pancake (Eng), B. Smart (Eng), J. Wu (Eng) • Manchester University • Michiel Sanders (PD) 27 October 2003

  11. FSU contributions to STT • Project leadership: • Horst Wahl (since Sept 1996), project co-leader with Ulrich Heintz (since Aug. 1999) • Beam position issues: • Dan Karmgard, Terry Heuring, Henryk Piekarz, Horst Wahl • Queueing studies: • Sailesh Chopra, Terry Heuring, Brian Connolly, Stephan Linn • Conceptual STT design: • Terry Heuring, Henryk Piekarz, Horst Wahl • Physics studies: • Brian Connolly, Terry Heuring, Harrison Prosper, Horst Wahl • Performance studies: • Terry Heuring, Dan Karmgard, Harrison Prosper, Horst Wahl 27 October 2003

  12. FSU contributions to STT, cont’d • generation of look-up tables for hit filter: • Sailesh Chopra, Bill Lee, Jose Lazoflores, Daekwang Kau • design of STC firmware (VHDL) + help with STC design: • Reginald Perry, Shweta Lolage, Vindi Lalam • L1CTT broadcasting: • Brian Connolly, Stephan Linn • STT trigger simulation: • Todd Adams, Brian Connolly, Sailesh Chopra, Harrison Prosper, Silvia Tentindo-Repond, Daekwang Kau, Norm Buchanan • Downloading: • Bill Lee • monitoring: • Sailesh Chopra, Bill Lee, Silvia Tentindo-Repond 27 October 2003

  13. FSU contributions to STT, cont’d • STT Examine: • Susan Blessing, Harrison Prosper, Sinjini Sengupta • Procurement of components for STC, motherboards, LTB, LRB • Horst Wahl, Sherry Beasley • Infrastructure at DØ (racks, crates, ethernet connections, CPUs, powersupplies, VTM installation,..) • Bill Lee, Horst Wahl, José Lazoflores • Fake data sender – setting up, programming • Stephan Linn 27 October 2003

  14. Downloading and Monitoring • FSU(Bill Lee), with help from BU • STT Crate Initialization • Controlled via Power PC running vxWorks at power-up • Downloads (via C) lookup tables and DSP code and initializes the STT cards to a running state. • Can also be Initialized via Python for test purposes • EPICS STT board support package • Gathers information from cards for monitoring purposes • Runtime downloads via COMICS using trigger initialization parameters • STT Examine • Susan Blessing, Harrison Prosper, Sinjini Sengupta • will be part of triggerExamine package 27 October 2003

  15. System Integration • All hardware at hand • Five of six crates fully populated • A seventh crate will be added as a test stand, freeing the sixth crate. • D0 is presently in a shutdown. • Before the shutdown, two STT crates were included in several runs. • Presently able to run at global run rates for several hours. • All five crates can be included in the run at any time • Full track reconstruction • Output to L3 and L2 • Coming out of the shutdown, the STT crates should be included in all runs. • Full Commissioning almost complete. 27 October 2003

  16. Conclusions • The Silicon Track Trigger is crucial for a large part of the Run 2 physics program. • Higgs, top, B physics • Project almost complete! • All hardware for Run 2a at hand! • Sixth crate commissioned this week. • The STT will be taking data at the end of the shutdown. • FSU group has made and will continue to make substantial contributions to the STT. 27 October 2003

  17. 27 October 2003

  18. 4 H-Disks 12 F-Disks 6 Barrels Silicon Microstrip Tracker • 6 10-cm long barrels + 16 disks • 793,000 channels of electronics • SMT hit resolution ~10 m 27 October 2003

  19. The Central Fiber Tracker • Scintillating Fibers • Up to ||=1.7 • 20 cm < r < 51 cm • 8 double layers • CFT: 77,000 channels CFT 27 October 2003

  20. Motherboard and Communication Links • 9Ux400 mm VME64x-compatible • 3 33-MHz PCI busses for on-board communications • Data communicated between cards via point-to-point links (LVDS) (Link Transmitter and Receiver Cards) • Control signals sent over backplane using dedicated lines • VME bus used for Level 3 readout and initialization/monitoring Universe II PCI-PCI bridges 27 October 2003

  21. Fiber Road Card (FRC) Design • Receives tracks from L1 Central Track Trigger • Communicates with trigger framework via SCL receiver card • Transmits tracks and trigger info to other cards • Manages L3 buffering and readout via Buffer Controller (BC) daughter cards on each motherboard • Implemented in 6 Altera FPGA’s • FLEX 10k30E and 10k50E • 30/50 k gates • 24/40 k bits of RAM • 208/240 pins 27 October 2003

  22. Fiber Road Card (FRC) Design FRC Link Transmitter Board Link Receiver Board Buffer controller 27 October 2003

  23. Silicon Trigger Card (STC) Design • Performs Silicon clustering and cluster-road matching • Clusters Neighbouring SMT hits (axial and stereo) • Each STC processes 8 silicon inputs simultaneously • Axial clusters are matched to ±1mm-wide roads around each fiber track via precomputed LUT • Mask bad strips and apply pedestal/gain corrections (via LUTs) • Implemented in FPGAs • Main functionality implemented in XILINX VIRTEX XCV812E • ~ 800k gates • 1.1 Mbits of RAM • 560 pin BGA package • 3 PCI interfaces use Altera ACEX EP1K30 chips This project made possible with state-of-the-art FPGAs 27 October 2003

  24. Silicon Trigger Card (STC) Design Road LUT FPGA 27 October 2003

  25. Track Fit Card (TFC) Design • Performs final SMT cluster filtering and track fitting • Receives 2 CFT hits and axial SMT clusters in CFT road • Lookup table used to convert hardware to physical coordinates • Selects clusters closest to road center and performs linearized track fit using precomputed matrix elements stored in on-board LUT • Require hits in only 3 out of 4 silicon layers • Output to L2CTT via Hotlink cards • C code running on 8 DSPs: • TI TMS320C6203B fixed point DSP  • 300 Mhz • two independent 32-bit I/O busses • performs 16 bit multiply/32 bit add instructions • rated at 2400 MIPS 27 October 2003

  26. Track Fit Card (TFC) Design Matrix LUT Coordinate Conversion LUT Hotlink Card DSP 27 October 2003

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