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Probabilistic CMOS & Probabilistic Boolean Logic

Probabilistic CMOS & Probabilistic Boolean Logic. Zheng-Shan Yu & Ching-Yi Huang & Fox 2013/05/27. Outline. Introduction PCMOS PBL Previous work T distribution Research direction Future work. Design flow. RTL --------------> gate level-----> transistor level.

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Probabilistic CMOS & Probabilistic Boolean Logic

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  1. Probabilistic CMOS & Probabilistic Boolean Logic Zheng-Shan Yu & Ching-Yi Huang & Fox 2013/05/27

  2. Outline • Introduction • PCMOS • PBL • Previous work • T distribution • Research direction • Future work

  3. Design flow • RTL --------------> gate level-----> transistor level module adder(A, B, out); input A; input B; output [1:0] out; assign out = A + B; endmodule

  4. Primitive gates a a out out a out b b

  5. CMOS with noise • Input coupling NOT: Simultaneous switching noise Crosstalk Thermal noise

  6. CMOS with varying voltages Without noise Add noise Raise voltage to avoid noise

  7. Probability of correctness v.s. energy • Energy per switching: Energy ratio p

  8. Probabilistic Boolean logic • Probabilistic OR: ∨p ,AND: ∧p , NOT: ¬p • Example: ∨p , assume p=0.9

  9. Probabilistic Boolean logic (cont.) • A probabilistic Boolean formula & circuit: • F = (a ∧0.8 b)∨0.7(¬0.8 c) a n 0.8 b 0.7 0.8 c m

  10. Probabilistic Boolean logic (cont.) • OR: Pout = (1–Pa)x(1–Pb)x(1–p) + [1–(1–Pa)x(1–Pb)]x p • AND: Pout = Pa x Pb xp + (1 – PaxPb) x (1–p) • NOT: Pout = (1–Pin) x p + Pinx (1–p) Pa Pout p Pb Pa Pout p Pb p Pout Pin

  11. Probabilistic Boolean logic (cont.) • F = (a ∧0.8 b)∨0.7(¬0.8c) • P(n) = 1 x 1 x 0.8 + 0 x 0 x 0.2 = 0.8 • P(m) = 0 x 0.8 + 1 x 0.2 = 0.2 • P(F) = 0.2 x 0.8 x 0.3 + (1-0.8 x 0.2) x 0.7 = 0.636 1 n 0.8 1 0.7 F 0.8 1 m

  12. Probabilistic Boolean logic (cont.) • F = (a ∧0.8 b)∨0.7(¬0.8c) • When (AND,NOT,OR) = (C,C,C) (C,I,C) (I,I,C) (I,C,I), F=1 • The probability of each situation = 0.448, 0.112, 0.028, 0.048 • P(F=1) = 0.636 1 n 0.8 1 0.7 F 0.8 1 m

  13. Previous work • A Statistical Approach to Correctness Analysis for Probabilistic Boolean Circuits • Problem formulation: • Given a probabilistic Boolean circuit & an input pattern • Report the output probability of being 1 • Monte Carlo Method • Random Pattern Generation • Sampling Rule • Scoring • Error Estimation

  14. Previous work (cont.) • A Scalable Approach to Correctness Analysis for Probabilistic Boolean Circuits • Problem formulation: • Given a probabilistic Boolean circuit • Report the Correctness of the given circuit • Correctness:

  15. Previous work (cont.) • How to compute the area of this quarter circle if we do not know the function ? • Monte Carlo Method • Random Pattern Generation • Sampling Rule • Scoring • Error Estimation

  16. Previous work (cont.) probability RPG a Y 0.8 b 0.7 X c Z 0.9 ‧ ‧ ‧ 0.9 sampling result correct value simulation result super pattern input pattern -sample gate-sample

  17. T distribution • Observe the behavior of PBC

  18. T distribution (cont.) • Confidence interval • (Error rate) 90%

  19. Research direction • Problem formulation: • Given a deterministic Boolean circuit and a correctness(energy) constraint • Report a low-energy-consumption(high-correctness) probabilistic Boolean circuit satisfying the correctness(energy) constraint

  20. Research direction (cont.) • Assign probability parameters • Low testability? A x C y B 0.9 F z A x 0.9 C y B F z

  21. Research direction (cont.) • Correctness vs #p-gatescurve % %

  22. Research direction (cont.) • Correctness vs #p-gatescurve via observability %

  23. Research direction (cont.) • Correctness vs #p-gatescurve via levels %

  24. Future work • Correctness • Know the behavior of PBCs • Design a method of assigning probability parameters • Energy • Design an energy model • Study the fundamental parts of PCMOS

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