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High-Performance Packet Classification for Multithreaded IXP Processors

This paper presents an efficient packet classification algorithm optimized for multithreaded network processors, specifically the Intel IXP 2800. By employing a compression technique on cross-producting tables, the algorithm reduces data redundancy significantly while achieving high classification speeds of 10 Gbps or more. The two-phase reduction tree effectively organizes data chunks derived from source and destination IP addresses, as well as port numbers, to enhance processing efficiency. Implementation issues such as memory space reduction, instruction selection, and latency hiding are also addressed, demonstrating the algorithm's robustness.

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High-Performance Packet Classification for Multithreaded IXP Processors

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  1. High-performance packet classification algorithm for multithreaded IXP network processor Authors: Duo Liu, Zheng Chen, Bei Hua, Nenghai Yu, Xinan Tang Presenter: Fang-Chen, Kuo Date: 2008/07/09 Publisher/Conf. : ACM Transactions on Embedded Computing Systems (TECS) 2008 Dept. of Computer Science and Information Engineering National Cheng Kung University, Taiwan R.O.C.

  2. Classification Scheme • Apply a compression technique to RFC’s cross-producting tables to reduce the data redundancies; • Exploit the NPU architectural features to achieve high classification speed, especially at 10 Gbps or higher on Intel IXP 2800.

  3. Reduction Tree (1) • Phase 0 contains 6 chunks: • chunk 0 uses the high 16 bits of source IP address, chunk 1 uses the low 16 bits of source IP address, • chunk 2 uses the high 16 bits of destination IP address, chunk 3 uses the low 16 bits of destination IP address, • chunk 4 uses source port, and chunk 5 uses destination port; • Phase 1 contains 2 chunks: • Chunk 0 (CPT X) of phase 1 is formed by combining chunk 0, 1, 4 of phase 0; • Chunk 1 (CPT Y) of phase 1 formed by combining chunk 2, 3, 5 of phase 0; • Phase 2 contains 1 chunk: • Chunk 0 (CPT Z) of phase 2 is formed by combining the two chunks of phase 1.

  4. Reduction Tree (2) Phase_0 Phase_1 Phase_2 SA_H16 SA_L16 CPT-X SP CPT_Z DA_H16 DA_L16 CPT_Y DP

  5. Bitmap-RFC

  6. Data structure for Bitmap-RFC algorithm

  7. Implementation Issues • Memory Space Reduction • Instruction Selection • POP_COUNT • Multiplication Elimination • Data Allocation • Task partitioning • Latency Hiding

  8. Experiment: Memory Requirement

  9. Experiment:Classifying Rates (1)

  10. Experiment:Classifying Rates (2)

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