1 / 15

Traffic Lights

Traffic Lights . Discussion D8.3a. Present state Next state. State Q2 Q1 Q0 D2 D1 D0. D0. Q0. s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1

newman
Télécharger la présentation

Traffic Lights

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Traffic Lights Discussion D8.3a

  2. Present state Next state State Q2 Q1 Q0 D2 D1 D0 D0 Q0 s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1 s3 0 1 1 1 0 0 s4 1 0 0 1 0 1 s5 1 0 1 1 1 0 s6 1 1 0 1 1 1 s7 1 1 1 0 0 0 D1 Q1 D2 Q2 Recall Divide-by-8 Counter Use Q2, Q1, Q0 as inputs to a combinational circuit to produce an arbitrary waveform.

  3. Blink State Q2 Q1 Q0 D2 D1 D0 y s0 0 0 0 0 0 1 1 s1 0 0 1 0 1 0 1 s2 0 1 0 0 1 1 0 s3 0 1 1 1 0 0 1 s4 1 0 0 1 0 1 0 s5 1 0 1 1 1 0 1 s6 1 1 0 1 1 1 0 s7 1 1 1 0 0 0 0

  4. lights.v module lights ( clr ,RYG ,clk ); input clr ; // pushbutton switch S4 - pin 69 wire clr ; input clk ; // 1 Hz clock - pin 12 wire clk ; output [5:0] RYG ; // RYGRYG reg [5:0] RYG ; reg [3:0] Q; // 4-bit counter always @(posedge clk or posedge clr) if(clr == 1) Q <= 0; else Q <= Q + 1;

  5. lights.v // Traffic lights always @(Q[3:1]) case(Q[3:1]) // RYGRYG 0: RYG = 6'b001100; 1: RYG = 6'b001100; 2: RYG = 6'b010100; 3: RYG = 6'b100100; 4: RYG = 6'b100001; 5: RYG = 6'b100001; 6: RYG = 6'b100010; 7: RYG = 6'b100100; default: RYG = 6'b001100; endcase endmodule

  6. lights.ucf #PACE: Start of PACE I/O Pin Assignments NET "clk" LOC = "p12" ; NET "clr" LOC = "p69" ; NET "RYG<0>" LOC = "p32" ; NET "RYG<1>" LOC = "p31" ; NET "RYG<2>" LOC = "p26" ; NET "RYG<3>" LOC = "p25" ; NET "RYG<4>" LOC = "p20" ; NET "RYG<5>" LOC = "p13" ;

  7. G3VM-61A1 MOS FET Relay

  8. Silicon-Controlled Rectifier (SCR) Text: Section 11-12, pages 446 - 449

  9. Triac

  10. Using an AC Relay

More Related