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Sequential Logic

Sequential Logic. Latches and Flip-Flops. Sequential Logic Circuits. The output of sequential logic circuits depends on the past history of the state of the outputs. Therefore, it incorporate a memory element (circuits must remember the past states of their outputs).

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Sequential Logic

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  1. Sequential Logic Latches and Flip-Flops

  2. Sequential Logic Circuits • The output of sequential logic circuits depends on the past history of the state of the outputs. • Therefore, it incorporate a memory element (circuits must remember the past states of their outputs). • Main characteristic of these circuits  feedback • An output logic level is treated just like another input to the circuit.

  3. Sequential Logic Circuits • Latches • Flip-flops

  4. The S-R (SET-RESET) Latch

  5. The S-R (SET-RESET) Latch Negative-OR equivalent of the NAND gate \S-\R latch

  6. The S-R (SET-RESET) Latch

  7. The S-R (SET-RESET) Latch

  8. The S-R (SET-RESET) Latch

  9. An Application of Latch

  10. The Gated S-R Latch

  11. The Gated S-R Latch

  12. The Gated D Latch

  13. The Gated D Latch

  14. Flip-Flops • Flip-flops are synchronous bistable devices. • Synchronous means that the output changes state only at a specified point on the triggering input called the clock (CLK). • Changes in the output occur in synchronization with the clock.

  15. Edge-Triggered FFs

  16. Edged-Triggered S-R FF

  17. Edged-Triggered S-R FF

  18. Edged-Triggered S-R FF

  19. Edge-Triggered D FF

  20. Edge-Triggered D FF

  21. Edge-Triggered JK-FF • JK-FF is versatile and is a widely used type of flip-flop. • The functioning of the JK-FF is identical to that of the SR-FF in the SET, RESET, and NC. • The difference is that the JK-FF has NO invalid state as does the SR-FF.

  22. Edge-Triggered JK-FF

  23. Edge-Triggered JK-FF

  24. Edge-Triggered JK-FF

  25. Asynchronous Preset and Clear Inputs • Most IC flip-flops have asynchronous inputs. • These are inputs that affect the state of the FF independent of the clock. • Preset (PRE) or direct set (SD) • Clear (CLR) or direct reset (RD) Logic symbol for a J-K flip-flop active-LOW preset and clear inputs.

  26. Edge-triggered JK-FF with PRE and CLR Toggle mode example

  27. Flip-Flop Applications • Parallel data storage

  28. Flip-Flop Applications • Frequency division

  29. Flip-Flop Applications • Frequency division

  30. Flip-Flop Applications • Counting

  31. Flip-Flop Applications • Counting

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