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Understanding the Fetch-Execute Cycle in Control Units

This document explains the Fetch-Execute cycle of a control unit in computer architecture. It details how the control unit sets up the address bus by transferring the contents of the Program Counter (PC) to the Memory Address Register (MAR). The document outlines the memory read operation, including activating the READ line, transferring memory contents to the Memory Data Register (MDR), and transferring data to the Accumulator if necessary. Additionally, it describes the memory write operation, encompassing data transfers from the MDR to memory, facilitated by the WRITE line activation.

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Understanding the Fetch-Execute Cycle in Control Units

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  1. The Fetch – Execute Cycle The control unit sets up the address bus by transferring the contents of the PC to the MAR The control unit activates the READ line on the control bus and the contents of the memory location are transferred to the MDR The control unit decodes and executes the instruction The instruction is transferred to the IR in the control unit The PC is incremented

  2. Memory Read Operation • The control unit sets up the address bus by transferring the memory address to be accessedto the MAR • The control unit activates the READ line on the control bus andthe contents of the memory location are transferred to the MDR • If necessary the contents of the MDR are transferred to the Accumulator

  3. Memory Write Operation • The control unit sets up the address bus by transferring the memory address to be accessedto the MAR • Set up data bus by transferring data to the MDR • The control unit activates the WRITE line on the control bus and the contents of the MDR are transferred to the memory location

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